公开(公告)号：US10115606B2

公开(公告)日：2018-10-30

申请号：US15139265

申请日：2016-04-26

申请人： Intel Corporation

发明人： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

公开(公告)号：US09704767B1

公开(公告)日：2017-07-11

申请号：US14998368

申请日：2015-12-23

申请人： Intel Corporation

发明人： Suriyakala Ramalingam ,  Yiqun Bai ,  Nisha Ananthakrishnan ,  Arjun Krishnan

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L21/4853 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

摘要： Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).

公开(公告)号：US09640415B2

公开(公告)日：2017-05-02

申请号：US14556994

申请日：2014-12-01

申请人： Intel Corporation

发明人： Randall D Lowe, Jr. ,  Suriyakala Suriya Ramalingam ,  Nisha Ananthakrishnan ,  James C. Matayabas, Jr. ,  Arjun Krishnan ,  Hitesh Arora

IPC分类号： H01L21/56 ,  H01L23/29 ,  H01L23/544 ,  C09D11/101 ,  C09D11/20

CPC分类号： H01L21/56 ,  C09D11/101 ,  C09D11/20 ,  H01L23/296 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

公开(公告)号：US09431274B2

公开(公告)日：2016-08-30

申请号：US13722886

申请日：2012-12-20

申请人： Intel Corporation

发明人： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC分类号： H01L21/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08900919B2

公开(公告)日：2014-12-02

申请号：US13801059

申请日：2013-03-13

申请人： Intel Corporation

发明人： Randall D. Lowe, Jr. ,  Suriyakala Suriya Ramalingam ,  Nisha Ananthakrishnan ,  James C. Matayabas, Jr. ,  Arjun Krishnan ,  Hitesh Arora

IPC分类号： H01L21/44 ,  H01L23/02 ,  H01L23/28 ,  C09D11/107

CPC分类号： H01L21/56 ,  C09D11/101 ,  C09D11/20 ,  H01L23/296 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

摘要翻译： 本文公开了在光引发剂存在下使用UV诱导的聚合方法将聚丙烯酸酯聚合物共价且不可分割地锚定到氧化物表面的方法。 通过该方法制备的方法和组合物可用作用于微电子封装的不可擦除的标记材料，以及用作焊料和密封剂屏障以防止液体在微电子封装的氧化物表面上的过度扩散。 在通过连接剂与丙烯酸酯反应性基团键合的作为第一结构域的氧化物反应性甲硅烷基的粘合促进剂的印刷和UV固化过程中，聚丙烯酸酯聚合物共价连接到氧化物表面。

公开(公告)号：US20240222274A1

公开(公告)日：2024-07-04

申请号：US18147820

申请日：2022-12-29

申请人： Intel Corporation

发明人： Praneeth Kumar Akkinepally ,  Sivakumar Nagarajan ,  Nisha Ananthakrishnan ,  Santosh Shaw ,  Wei Gao

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06541

摘要： Integrated circuit (IC) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, an IC die may include a substrate, a front-end-of-line (FEOL) layer over the substrate, where the FEOL layer includes a plurality of transistors, a first back-end-of-line (BEOL) layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.

公开(公告)号：US11804470B2

公开(公告)日：2023-10-31

申请号：US16548255

申请日：2019-08-22

申请人： Intel Corporation

发明人： Xavier F. Brun ,  Kaizad Mistry ,  Paul R. Start ,  Nisha Ananthakrishnan ,  Yawei Liang ,  Jigneshkumar P. Patel ,  Sairam Agraharam ,  Liwei Wang

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/73253

摘要： Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

公开(公告)号：US20160168351A1

公开(公告)日：2016-06-16

申请号：US15047866

申请日：2016-02-19

申请人： Intel Corporation

发明人： Yonghao Xiu ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Arjun Krishnan

IPC分类号： C08K3/00 ,  H01L23/29 ,  H01L21/56

CPC分类号： C08K3/013 ,  H01L21/563 ,  H01L23/295 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0493 ,  H01L2924/053 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/186 ,  H01L2924/0665 ,  H01L2924/05032 ,  H01L2924/014

摘要： An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

申请人： Intel Corporation

发明人： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC分类号： H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

摘要： Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20170170088A1

公开(公告)日：2017-06-15

申请号：US15037851

申请日：2015-06-17

申请人： Intel Corporation

发明人： Venmathy McMahan ,  Sivakumar Nagarajan ,  Elah Bozorg-Grayeli ,  Amrita Mallik ,  Kuang-Han Chu ,  Liwei Wang ,  Nisha Ananthakrishnan ,  Craig J. Weinman ,  Amram Eitan

IPC分类号： H01L23/29 ,  H01L23/18 ,  H01L23/31

摘要： Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.