公开(公告)号：US10310989B2

公开(公告)日：2019-06-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US09934859B1

公开(公告)日：2018-04-03

申请号：US15391763

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Prashant S. Damle ,  Kunal A. Khochare ,  Philip Hillier ,  Jeffrey W. Ryden ,  Richard P. Mangold

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.

公开(公告)号：US20190102320A1

公开(公告)日：2019-04-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US09691492B1

公开(公告)日：2017-06-27

申请号：US15280669

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Zion S. Kwok ,  Christopher F. Connor ,  Philip Hillier ,  Jeffrey W. Ryden

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/10 ,  G11C16/20 ,  G11C16/30

Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.