公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC: B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC classification number: B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20230091834A1

公开(公告)日：2023-03-23

申请号：US17482380

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Ala OMER ,  Sarah BLYTHE ,  Junxin WANG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Jieying KONG

IPC: G02B6/125 ,  G02B6/13

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230090188A1

公开(公告)日：2023-03-23

申请号：US17481001

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Junxin WANG ,  Kemal AYGUN ,  Jieying KONG ,  Ala OMER ,  Whitney M. BRYKS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: An apparatus is described. The apparatus includes a semiconductor chip package substrate having alternating metal and dielectric layers. First and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of 1 ns or less.

公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC: G02B6/43 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.