公开(公告)号：US20240213328A1

公开(公告)日：2024-06-27

申请号：US18089494

申请日：2022-12-27

申请人： INTEL CORPORATION

发明人： Vinith BEJUGAM ,  Yonggang LI ,  Srinivas V. PIETAMBARAM ,  Chandrasekharan NAIR ,  Whitney BRYKS ,  Gene CORYELL

IPC分类号： H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L29/1606 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L2924/15311

摘要： Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.

公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

申请人： INTEL CORPORATION

发明人： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC分类号： B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC分类号： B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

摘要： Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20230294204A1

公开(公告)日：2023-09-21

申请号：US17698024

申请日：2022-03-18

申请人： Intel Corporation

发明人： Jeremy ECTON ,  Vinith BEJUGAM ,  Jefferson KAPLAN ,  Yonggang LI ,  Whitney BRYKS ,  Samuel GEORGE ,  Jeremy CROSS

IPC分类号： B23K26/142 ,  B23K26/08 ,  B08B3/08

CPC分类号： B23K26/142 ,  B23K26/0823 ,  B08B3/08

摘要： A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent. The method further includes removing the substrate from the solvent into which the residue is moved.

公开(公告)号：US20240188225A1

公开(公告)日：2024-06-06

申请号：US18060598

申请日：2022-12-01

申请人： Intel Corporation

发明人： Vinith BEJUGAM ,  Rengarajan SHANMUGAM ,  Srinivas PIETAMBARAM ,  Mao-Feng TSENG ,  Yonggang LI

IPC分类号： H05K3/40 ,  C23C18/18 ,  C23C18/38 ,  H05K1/03 ,  H05K1/11 ,  H05K3/18

CPC分类号： H05K3/4038 ,  C23C18/1868 ,  C23C18/38 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/181 ,  H05K2201/09563 ,  H05K2201/2081 ,  H05K2203/107

摘要： A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

公开(公告)号：US20240079530A1

公开(公告)日：2024-03-07

申请号：US17903126

申请日：2022-09-06

申请人： Intel Corporation

发明人： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Nicholas HAEHN ,  Andrea NICOLAS FLORES ,  Ali LEHAF ,  Benjamin DUONG ,  Joshua STACEY

IPC分类号： H01L33/48 ,  H01L33/00 ,  H01L33/60 ,  H01L33/62

CPC分类号： H01L33/486 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L2933/0058 ,  H01L2933/0066

摘要： Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

公开(公告)号：US20230361002A1

公开(公告)日：2023-11-09

申请号：US17738085

申请日：2022-05-06

申请人： Intel Corporation

发明人： Vinith BEJUGAM ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Samuel GEORGE ,  Srinivas PIETAMBARAM

IPC分类号： H01L23/48 ,  H01L23/15 ,  H01L21/48 ,  H01L21/68

CPC分类号： H01L23/481 ,  H01L23/15 ,  H01L21/486 ,  H01L21/68

摘要： The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

公开(公告)号：US20240215163A1

公开(公告)日：2024-06-27

申请号：US18089489

申请日：2022-12-27

申请人： Intel Corporation

发明人： Onur OZKAN ,  Jacob VEHONSKY ,  Vinith BEJUGAM ,  Nicholas S. HAEHN ,  Andrea NICOLAS FLORES ,  Mao-Feng TSENG

IPC分类号： H05K1/11 ,  H05K1/03 ,  H05K1/18

CPC分类号： H05K1/112 ,  H05K1/0306 ,  H05K1/183 ,  H01L23/49838

摘要： Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.

公开(公告)号：US20240178157A1

公开(公告)日：2024-05-30

申请号：US18071257

申请日：2022-11-29

申请人： Intel Corporation

发明人： Vinith BEJUGAM ,  Whitney BRYKS ,  Brandon C. MARIN ,  Vishal Bhimrao ZADE ,  Deniz TURAN ,  Srinivas V. PIETAMBARAM

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L23/49822

摘要： Embodiments disclosed herein include package substrates. In a particular embodiment, the package substrate comprises a core. The core may be a glass core. In an embodiment, buildup layers are provided over the core, and a shape memory polymer (SMP) is provided over the core.

公开(公告)号：US20240079259A1

公开(公告)日：2024-03-07

申请号：US17901894

申请日：2022-09-02

申请人： Intel Corporation

发明人： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Andrea NICOLAS ,  Nicholas HAEHN

IPC分类号： H01L21/683 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67

CPC分类号： H01L21/6835 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67121 ,  B32B17/06 ,  H01L2221/68345

摘要： The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.