-
公开(公告)号:US20240217216A1
公开(公告)日:2024-07-04
申请号:US18091028
申请日:2022-12-29
申请人: INTEL CORPORATION
发明人: Kristof DARMAWIKARTA , Tarek A. IBRAHIM , Srinivas V. PIETAMBARAM , Dilan SENEVIRATNE , Jieying KONG , Thomas HEATON , Whitney BRYKS , Vinith BEJUGAM , Junxin WANG , Gang DUAN
CPC分类号: B32B17/10642 , B32B7/12 , B32B17/02 , B65D85/48 , B32B2260/04 , B32B2307/202 , B32B2457/00
摘要: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
-
公开(公告)号:US20230294204A1
公开(公告)日:2023-09-21
申请号:US17698024
申请日:2022-03-18
申请人: Intel Corporation
发明人: Jeremy ECTON , Vinith BEJUGAM , Jefferson KAPLAN , Yonggang LI , Whitney BRYKS , Samuel GEORGE , Jeremy CROSS
IPC分类号: B23K26/142 , B23K26/08 , B08B3/08
CPC分类号: B23K26/142 , B23K26/0823 , B08B3/08
摘要: A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent. The method further includes removing the substrate from the solvent into which the residue is moved.
-
公开(公告)号:US20240153857A1
公开(公告)日:2024-05-09
申请号:US17983230
申请日:2022-11-08
申请人: Intel Corporation
发明人: Bainye Francoise ANGOUA , Whitney BRYKS , Yosef KORNBLUTH , Daniel ROSALES-YEOMANS , Holly CLINGAN , Patrick QUACH , Jade Sharee LEWIS , Aaditya Anand CANDADAI
IPC分类号: H01L23/498 , H01L23/15 , H01L23/544
CPC分类号: H01L23/49827 , H01L23/15 , H01L23/49822 , H01L23/544 , H01L24/16 , H01L2223/54426 , H01L2224/16225
摘要: Embodiments disclose a package substrate. In an embodiment, the package substrate comprises a core, where the core comprises: a first sub-core, where the first sub-core comprises a glass and a first through glass via (TGV), and a second sub-core, where the second sub-core comprises the glass and a second TGV. In an embodiment, the first TGV directly contacts the second TGV.
-
公开(公告)号:US20230091834A1
公开(公告)日:2023-03-23
申请号:US17482380
申请日:2021-09-22
申请人: Intel Corporation
发明人: Bainye Francoise ANGOUA , Ala OMER , Sarah BLYTHE , Junxin WANG , Whitney BRYKS , Dilan SENEVIRATNE , Jieying KONG
摘要: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.
-
公开(公告)号:US20240213328A1
公开(公告)日:2024-06-27
申请号:US18089494
申请日:2022-12-27
申请人: INTEL CORPORATION
发明人: Vinith BEJUGAM , Yonggang LI , Srinivas V. PIETAMBARAM , Chandrasekharan NAIR , Whitney BRYKS , Gene CORYELL
IPC分类号: H01L29/16 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/48
CPC分类号: H01L29/1606 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/16 , H01L2924/15311
摘要: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.
-
公开(公告)号:US20240177907A1
公开(公告)日:2024-05-30
申请号:US18059992
申请日:2022-11-30
申请人: Intel Corporation
发明人: Yosef KORNBLUTH , Whitney BRYKS , Ravindranadh ELURI , Aaditya Anand CANDADAI , Srinivas PIETAMBARAM
摘要: The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.
-
公开(公告)号:US20230187331A1
公开(公告)日:2023-06-15
申请号:US17549497
申请日:2021-12-13
申请人: Intel Corporation
IPC分类号: H01L23/498 , H01L21/48 , H01L23/15
CPC分类号: H01L23/49827 , H01L21/486 , H01L23/15 , H01L23/49838 , H01L23/49866
摘要: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.
-
公开(公告)号:US20240203664A1
公开(公告)日:2024-06-20
申请号:US18081362
申请日:2022-12-14
申请人: Intel Corporation
发明人: Yosef KORNBLUTH , Bainye Francoise ANGOUA , Whitney BRYKS , Daniel ROSALES-YEOMANS , Aaditya Anand CANDADAI , Holly CLINGAN , Jade Sharee LEWIS , Patrick QUACH , Srinivas V. PIETAMBARAM
摘要: Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.
-
公开(公告)号:US20240092074A1
公开(公告)日:2024-03-21
申请号:US17949276
申请日:2022-09-21
申请人: Intel Corporation
发明人: Joshua STACEY , Yosef KORNBLUTH , Whitney BRYKS
CPC分类号: B32B41/00 , B32B37/06 , B32B37/08 , B32B37/10 , H01L21/4846 , B32B2309/022 , B32B2309/105 , B32B2309/12 , B32B2309/72 , B32B2457/00
摘要: The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.
-
10.
公开(公告)号:US20230420348A1
公开(公告)日:2023-12-28
申请号:US17852039
申请日:2022-06-28
申请人: Intel Corporation
IPC分类号: H01L23/498 , H01L21/48
CPC分类号: H01L23/49822 , H01L23/49894 , H01L21/4857 , H01L2224/16225 , H01L24/16
摘要: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.
-
-
-
-
-
-
-
-
-