公开(公告)号：US20230099632A1

公开(公告)日：2023-03-30

申请号：US17485248

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L27/02

Abstract: Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.

公开(公告)号：US20210066162A1

公开(公告)日：2021-03-04

申请号：US16557896

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Sergio A. CHAN ARGUEDAS ,  Nicholas S. HAEHN ,  Edvin CETEGEN ,  Nicholas NEAL ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON ,  Vipul MEHTA

IPC: H01L23/42 ,  H01L23/00

Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

公开(公告)号：US20230089093A1

公开(公告)日：2023-03-23

申请号：US17482804

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Krishna BHARATH ,  Bharat PENMECHA ,  Anderw COLLINS ,  Kaladhar RADHAKRISHNAN ,  Sriram SRINIVASAN

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20230097236A1

公开(公告)日：2023-03-30

申请号：US17485287

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Aleksandar ALEKSOV ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Telesphor KAMGAING ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises: a core substrate. In an embodiment, the core substrate comprises glass. In an embodiment, a via passes through the core substrate. In an embodiment, a die is coupled to the package substrate, where the die comprises an IO interface. In an embodiment, the IO interface is electrically coupled to the via and the via is within a footprint of the die.

公开(公告)号：US20230091050A1

公开(公告)日：2023-03-23

申请号：US17479031

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Pooya TADAYON ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Changhua LIU ,  Kemal AYGÜN

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210035818A1

公开(公告)日：2021-02-04

申请号：US16525985

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Wei-Lun K. JEN ,  Steve S. CHO ,  Jason M. GAMBA ,  Javier SOTO GONZALEZ

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US20230090759A1

公开(公告)日：2023-03-23

申请号：US17482747

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Andrew COLLINS

IPC: H01L23/64 ,  H01L23/14 ,  H01L23/48 ,  H01L21/50 ,  H01F3/02 ,  H01F3/10

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

公开(公告)号：US20230089096A1

公开(公告)日：2023-03-23

申请号：US17481234

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Sanka GANESAN ,  Tarek A. IBRAHIM ,  Russell MORTENSEN

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.

公开(公告)号：US20230086356A1

公开(公告)日：2023-03-23

申请号：US17481237

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Sanka GANESAN ,  Ram S. VISWANATH

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.

公开(公告)号：US20230085944A1

公开(公告)日：2023-03-23

申请号：US17482843

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Bai NIE ,  Brandon C. MARIN ,  Sandeep B. SANE ,  Leonel ARANA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises an organic material. In an embodiment, a via is provided through a thickness of the core. In an embodiment, a shell is around the via, where the shell comprises a magnetic material. In an embodiment, a mold layer is over the core, and a bridge is embedded in the mold layer. In an embodiment, a column is through the mold layer, where the column is aligned with the via.