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1.
公开(公告)号:US20200233717A1
公开(公告)日:2020-07-23
申请号:US15755216
申请日:2017-03-28
Applicant: INTEL CORPORATION
Inventor: Ned M. SMITH , Changzheng WEI , Songwu SHEN , Ziye YANG , Junyuan WANG , Weigang LI , Wenqian YU
Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).
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2.
公开(公告)号:US20240296137A1
公开(公告)日:2024-09-05
申请号:US18647547
申请日:2024-04-26
Applicant: Intel Corporation
Inventor: Junyuan WANG , Maksim LUKOSHKOV , Weigang LI , Xin ZENG
IPC: G06F13/42
CPC classification number: G06F13/4221 , G06F2213/0024
Abstract: Techniques to improve device scalability using a peer-to-peer protocol over a communication link. The techniques can include use of an input/output (IO) device access instruction set architecture (ISA) command to place an IO job request through an agent device from a host processor to a device, the host processor, agent device and device coupled to a communication link switch. The IO job request can be communicated through the communication link switch.
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公开(公告)号:US20210203491A1
公开(公告)日:2021-07-01
申请号:US16649192
申请日:2017-12-29
Applicant: INTEL CORPORATION
Inventor: Changzheng WEI , Junyuan WANG , Ned SMITH , Weigang LI , Ping YU
Abstract: Technologies for key management of internet-of-things (IoT) devices include an IoT device, an authority center server, and a group management server. The IoT device is configured to authenticate with an authority center server via an offline communication channel, receive a group member private key as a function of the authentication with the authority center server, and authenticate with a group management server via a secure online communication channel using the group member private key. The IoT device is further configured to receive a group shared key as a function of the authentication with the group management server, encrypt secret data with the group shared key, and transmit the encrypted secret data to the group management server. Other embodiments are described herein.
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公开(公告)号:US20220295160A1
公开(公告)日:2022-09-15
申请号:US17830223
申请日:2022-06-01
Applicant: Intel Corporation
Inventor: Junyuan WANG , Timothy WAITE , Ziye YANG , Zijuan FAN , Yao HUO , Weigang LI , Yuze XIAO , Greg THOMAS , Qianjun XIE
Abstract: Examples described herein relate to circuitry to provide telemetry data of first circuitry based on a power state of the first circuitry and provide telemetry data of second circuitry based on a power state of the second circuitry.
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公开(公告)号:US20240118913A1
公开(公告)日:2024-04-11
申请号:US18283205
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Kaijie GUO , Junyuan WANG , Maksim LUKOSHKOV , Weigang LI , Xin ZENG
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/45579 , G06F2009/45583 , G06F2009/45591
Abstract: An apparatus and method to implement shared virtual memory in a trust zone. For example, one embodiment of a processor comprises: a plurality of cores; a memory controller coupled to the plurality of cores to establish a first private memory region in a system memory using a first key associated with a first trust domain of a first guest; an input/output memory management unit (IOMMU) coupled to the memory controller, the IOMMU to receive a memory access request by an input/output (IO) device, the memory access request comprising a first address space identifier and a guest virtual address (GVA), the IOMMU to access an entry in a first translation table using at least the first address space identifier to determine that the memory access request is directed to the first private memory region which is not directly accessible to the IOMMU, the IOMMU to generate an address translation request associated with the memory access request, wherein based on the address translation request, a virtual machine monitor (VMM) running on one or more of the plurality of cores is to initiate a secure transaction sequence with trust domain manager to cause a secure entry into the first trust domain to translate the GVA to a physical address based on the address space identifier, the IOMMU to receive the physical address from the VMM and to use the physical address to perform the requested memory access on behalf of the IO device.
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6.
公开(公告)号:US20240020241A1
公开(公告)日:2024-01-18
申请号:US18254322
申请日:2020-12-24
Applicant: Intel Corporation
Inventor: Kaijie GUO , Weigang LI , Junyuan WANG , Bo CUI , Mithilesh K. DAS , Amit K. WARDHAN , Zijuan FAN , Maojun JI , Qianjun XIE , Tingqiang CHU
IPC: G06F12/1081
CPC classification number: G06F12/1081 , G06F2212/657
Abstract: Apparatus and method for performing address pre-translation to enhance direct memory access by hardware subsystems is described herein. An apparatus embodiment includes a processor to execute an enqueue instruction to submit, to a hardware subsystem, a job descriptor describing a job to be performed. The job descriptor includes virtual addresses of memory locations in which data required to perform the job are stored. An input-output memory management unit (IOMMU) is to obtain the address translations for the virtual addresses responsive to a pre-translation request from the processor. The address translations is obtained by the IOMMU prior to receiving a memory access request from the hardware subsystem. The IOMMU is to retrieve the data from the memory location using the address translations and to provide the retrieved data to the hardware subsystem to fulfill the request.
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公开(公告)号:US20220360279A1
公开(公告)日:2022-11-10
申请号:US17870427
申请日:2022-07-21
Applicant: Intel Corporation
Inventor: Xiaoyan BO , Junyuan WANG , Xinghong CHEN , Chengfei ZHU , Shuai YUAN , Weigang LI , Dongsheng LIANG , Fei YU
Abstract: Examples described herein relate to performing data compression by performing dictionary matching of data using hardware circuitry to generate dictionary matched results and post-processing of dictionary matched results using software executed by a processor. In some examples, dictionary matching includes LZ77 dictionary matching. In some examples, dictionary matching occurs on multiple segments of data in parallel.
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公开(公告)号:US20210019172A1
公开(公告)日:2021-01-21
申请号:US17042114
申请日:2018-06-28
Applicant: INTEL CORPORATION
Inventor: Baiju V. PATEL , Kapil SOOD , Weigang LI , Ping YU , Changzheng WEI , Junyuan WANG , Xin ZENG
Abstract: A cryptographic data item utilized to derive a first cryptographic key employed by a first memory controller for implementing a first cryptographically protected execution environment for storing memory pages associated with a virtual machine may be received from a first host system via a first secure communication channel. The cryptographic data item may be transmitted to a second host system via a second secure communication channel for implementing a second cryptographically protected environment on the second host system. The first host system may be caused to migrate the memory pages of the virtual machine via an unsecured communication channel to the second host system for storing in the second cryptographically protected execution environment.
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公开(公告)号:US20240243913A1
公开(公告)日:2024-07-18
申请号:US18560368
申请日:2021-11-23
Applicant: Intel Corporation
Inventor: Junyuan WANG , Kapil SOOD , Brian WILL , Thomas Joseph O'DWYER , Zijuan FAN , Kaijie GUO , Maksim LUKOSHKOV , Seosamh O'RIORDAIN , Jun XU , Guodong ZHU , Siming WAN
IPC: H04L9/30
CPC classification number: H04L9/3066 , H04L9/302
Abstract: Methods and apparatus for customers key protection for cloud native deployments. Compute resources for a compute platform comprising platform hardware including one or more processors are allocated to one or more customers that use the compute resources to execute applications and/or services used to perform customer workloads. The compute platform includes a per-part device key that is used to generate hardware protected key used by the applications and services. Mechanisms are provided to ensure hardware protected keys can only be accessed by associated customers and/or customer applications and services, while preventing other customers and/or applications and services from accessing the hardware protected keys. The hardware protected keys include keys employing various forms of RSA and ECC Wrapped Private Keys (WPKs) including RSA WPKs, RSA Chinese Remainder Theorem CRT WPK and ECC WPKs.
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公开(公告)号:US20240241831A1
公开(公告)日:2024-07-18
申请号:US18622745
申请日:2024-03-29
Applicant: Intel Corporation
Inventor: Junyuan WANG , Haoxiang SUN , Xin ZENG , Maksim LUKOSHKOV , Weigang LI , Zijuan FAN , Jun XU
IPC: G06F12/0862
CPC classification number: G06F12/0862 , G06F2212/602
Abstract: Techniques to reduce data processing latency for a device. Circuitry at a device coupled with a host processor can facilitate execution of parallel tasks associated with processing data for a service offloaded to the device from the host processor. The parallel tasks can include prefetching information for address translations related to a shared virtual memory (SVM) space that is shared between the device and the host processor and prefetching data to be processed by device in relation to the offloaded service.
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