公开(公告)号：US20160364143A1

公开(公告)日：2016-12-15

申请号：US15175697

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： RANDALL K. WEBB ,  JAWAD B. KHAN ,  RICHARD L. COULSON ,  KNUT S. GRIMSRUD ,  BRIAN M. YABLON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7201

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

公开(公告)号：US20170123703A1

公开(公告)日：2017-05-04

申请号：US15357783

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： JASON B. AKERS ,  KNUT S. GRIMSRUD ,  ROBERT J. ROYER, JR. ,  RICHARD P. MANGOLD ,  SANJEEV N. TRIKA

IPC: G06F3/06 ,  G11C7/10 ,  G11C14/00

CPC classification number: G06F3/0625 ,  G06F1/3287 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1417 ,  G11C5/148 ,  G11C7/1072 ,  G11C14/0009 ,  Y02D10/171

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

公开(公告)号：US20170262029A1

公开(公告)日：2017-09-14

申请号：US15068827

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： MICHAEL D. NELSON ,  JAWAD B. KHAN ,  RANDALL K. WEBB ,  KNUT S. GRIMSRUD ,  WAYNE J. ALLEN

IPC: G06F1/20 ,  H05K7/14

CPC classification number: G06F1/20 ,  H05K7/1439 ,  H05K7/1452 ,  H05K7/1457 ,  H05K7/1487

Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

公开(公告)号：US20160092361A1

公开(公告)日：2016-03-31

申请号：US14497392

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： KNUT S. GRIMSRUD ,  SANJEEV N. TRIKA

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0833 ,  G06F12/0238 ,  G06F12/0886 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/621 ,  H04N19/423

Abstract: Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof.

Abstract translation: 描述采用数据压缩的缓存技术。 本公开的技术包括缓存系统，方法和计算机可读介质，其中高速缓存行中的数据在被写入高速缓冲存储器之前被压缩。 在一些实施例中，在将压缩数据写入高速缓冲存储器之前，这些技术使得高速缓存控制器可以了解高速缓存行中的数据被压缩的程度。 因此，高速缓存控制器可以至少部分地基于压缩数据的大小，归因于压缩数据（或其对应的输入数据）的压缩率或其组合来确定压缩数据将被存储在高速缓冲存储器中的位置 。

公开(公告)号：US20150378814A1

公开(公告)日：2015-12-31

申请号：US14314181

申请日：2014-06-25

Applicant: Intel Corporation

Inventor： RANDALL K. WEBB ,  JAWAD B. KHAN ,  RICHARD L. COULSON ,  KNUT S. GRIMSRUD ,  BRIAN M. YABLON

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7201

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

Abstract translation: 本公开涉及可扩展存储器集线器。 装置可以包括第一可扩展非易失性存储器（NVM）集线器（EN集线器）。 第一个EN集线器包括被配置为将第一EN集线器耦合到NVM控制器或第二EN集线器的上游接口端口; 下游接口端口，被配置为将第一EN集线器耦合到第三EN集线器或NVM设备; 至少一个NVM设备端口，每个NVM设备端口被配置为经由NVM信道将所述第一EN集线器耦合到相应的NVM设备; 和一个EN集线器控制器。 EN集线器控制器包括命令逻辑，其被配置为响应于来自NVM控制器的初始化链命令初始化第一EN集线器，初始化包括枚举耦合到第一EN集线器的每个NVM设备以及一个或多个相关联的NVM管芯中的每一个。