公开(公告)号：US20150378814A1

公开(公告)日：2015-12-31

申请号：US14314181

申请日：2014-06-25

Applicant: Intel Corporation

Inventor： RANDALL K. WEBB ,  JAWAD B. KHAN ,  RICHARD L. COULSON ,  KNUT S. GRIMSRUD ,  BRIAN M. YABLON

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7201

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

Abstract translation: 本公开涉及可扩展存储器集线器。 装置可以包括第一可扩展非易失性存储器（NVM）集线器（EN集线器）。 第一个EN集线器包括被配置为将第一EN集线器耦合到NVM控制器或第二EN集线器的上游接口端口; 下游接口端口，被配置为将第一EN集线器耦合到第三EN集线器或NVM设备; 至少一个NVM设备端口，每个NVM设备端口被配置为经由NVM信道将所述第一EN集线器耦合到相应的NVM设备; 和一个EN集线器控制器。 EN集线器控制器包括命令逻辑，其被配置为响应于来自NVM控制器的初始化链命令初始化第一EN集线器，初始化包括枚举耦合到第一EN集线器的每个NVM设备以及一个或多个相关联的NVM管芯中的每一个。

公开(公告)号：US20190004726A1

公开(公告)日：2019-01-03

申请号：US15639450

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： PENG LI ,  JAWAD B. KHAN ,  SANJEEV N. TRIKA ,  VINODH GOPAL

IPC: G06F3/06

Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device. The device storage logic is further to set a descriptor pointer associated with the unique input KV data block to point to a physical nonvolatile memory (NVM) address associated with an existing unique data block and increment a first reference count associated with the existing unique data block, if the unique input KV data block is a duplicate of the existing unique data block, or store the input KV data block to a physical NVM location associated with a selected physical NVM address, set the descriptor pointer to point to the selected physical NVM address and set a second reference count associated with the selected physical NVM address to one, if the unique input KV data block is not duplicated in the NVM circuitry.

公开(公告)号：US20160364143A1

公开(公告)日：2016-12-15

申请号：US15175697

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： RANDALL K. WEBB ,  JAWAD B. KHAN ,  RICHARD L. COULSON ,  KNUT S. GRIMSRUD ,  BRIAN M. YABLON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7201

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

公开(公告)号：US20190079681A1

公开(公告)日：2019-03-14

申请号：US15699930

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： SANJEEV N. TRIKA ,  PENG LI ,  JAWAD B. KHAN

IPC: G06F3/06 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F12/1009

CPC classification number: G06F3/0616 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1036 ,  G11C29/52 ,  H03M13/2906

Abstract: One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LB As, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.

公开(公告)号：US20170091127A1

公开(公告)日：2017-03-30

申请号：US14866310

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： JAWAD B. KHAN ,  RANDALL K. WEBB ,  KELVIN D. GREEN ,  BRIAN R. MCFARLANE

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/102 ,  G06F13/4068 ,  G06F13/4282

Abstract: Examples may include techniques to couple with a storage device via multiple communication ports. A first communication port at the storage device may be configurable to couple with at least one other storage device, a field programmable gate array (FPGA)/programmable logic or application-specific integrated circuit (ASIC) via a serial communication link. A second communication port at the storage device is arranged to couple with a host computing device.

公开(公告)号：US20190044259A1

公开(公告)日：2019-02-07

申请号：US15807519

申请日：2017-11-08

Applicant: INTEL CORPORATION

Inventor： JAWAD B. KHAN ,  JORGE ULISES MARTINEZ ARAIZA ,  MICHAEL D. NELSON

IPC: H01R12/70 ,  H01R12/72 ,  H01R13/26 ,  H01R43/20 ,  H05K7/14

Abstract: Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector may include a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity may include first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity may further include a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch may define a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US20170262029A1

公开(公告)日：2017-09-14

申请号：US15068827

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： MICHAEL D. NELSON ,  JAWAD B. KHAN ,  RANDALL K. WEBB ,  KNUT S. GRIMSRUD ,  WAYNE J. ALLEN

IPC: G06F1/20 ,  H05K7/14

CPC classification number: G06F1/20 ,  H05K7/1439 ,  H05K7/1452 ,  H05K7/1457 ,  H05K7/1487

Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

公开(公告)号：US20160283159A1

公开(公告)日：2016-09-29

申请号：US14671929

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  JAWAD B. KHAN

IPC: G06F3/06 ,  G06F12/08 ,  H03M7/30

CPC classification number: G06F3/0638 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/401 ,  G06F2212/60 ,  H03M7/3086 ,  H03M7/3095 ,  H03M7/6058

Abstract: Compression and decompression technology within a solid-state device (SSD) is disclosed that provides a good compression ratio while taking up less on-chip area. An input interface receives an input stream to be compressed. An output interface provides a compressed stream. A history buffer is of a fixed size that is a fraction of a size of a data buffer. Processing logic encodes into the compressed stream element types, literals and pointers, the latter which reference copies of data found elsewhere within the history buffer during compression. The history buffer may be multiple banks in width, where the data is loaded from the input stream sequentially across rows of the banks. The decompression side may be similarly designed, optionally with a different number of banks. The pointers may be a fixed two bytes including four bits for length and eleven bits for offset of back reference to a copy (or other combination).

Abstract translation: 公开了在固态设备（SSD）中的压缩和解压缩技术，其提供了良好的压缩比，同时占用较少的片上区域。 输入接口接收要压缩的输入流。 输出接口提供压缩流。 历史缓冲区具有固定大小，它是数据缓冲区大小的一小部分。 处理逻辑编码为压缩流元素类型，文字和指针，后者在压缩期间引用历史缓冲区中其他位置的数据副本。 历史缓冲器可以是宽度的多个存储体，其中数据从输入流顺序地跨越存储体的行加载。 减压侧可以类似地设计，可选地具有不同数量的堤。 指针可以是固定的两个字节，包括用于长度的四个位和用于对拷贝（或其他组合）的反参考偏移的十一位）。