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公开(公告)号:US10970239B2
公开(公告)日:2021-04-06
申请号:US15970639
申请日:2018-05-03
Applicant: Intel Corporation
Inventor: Rajesh Bhaskar , Kenneth Foust , George Vergis
Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.
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公开(公告)号:US20220416428A1
公开(公告)日:2022-12-29
申请号:US17357658
申请日:2021-06-24
Applicant: Intel Corporation
Inventor: Zhen Zhou , Tae Young Yang , Shuhei Yamada , Tolga Acikalin , Johanny Escobar Pelaez , Kenneth Foust , Jason Mix , Renzhi Liu
Abstract: Various embodiments provide systems, devices, and methods for an antenna assembly included in an integrated circuit (IC) package. The antenna assembly may be used for near field wireless communication such as package-to-package and/or chip-to-chip communication. The antenna assembly may include a feed plate (e.g., a top feed) that is capacitively coupled to a first via and a second via. The feed plate may further be capacitively coupled to a loading structure. The first via may be conductively coupled to a ground potential. In some embodiments, the antenna assembly may further include a stub structure (e.g., an open stub or a short stub) that is conductively coupled to the second via. An impedance matching network may be coupled between the feed plate and an IC die that communicates using the antenna assembly. Other embodiments may be described and claimed.
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3.
公开(公告)号:US20170262395A1
公开(公告)日:2017-09-14
申请号:US15607341
申请日:2017-05-26
Applicant: INTEL CORPORATION
Inventor: Haran Thanigasalam , Kenneth Foust , Rajasekaran Andiappan
IPC: G06F13/364 , H04L29/06 , G06F13/42 , G06F13/24 , G06F13/16
CPC classification number: G06F13/364 , G06F13/1673 , G06F13/24 , G06F13/4282 , H04L63/0492
Abstract: Methods, apparati, systems for including interrupt functionality in sensor interconnects field are disclosed in the present disclosure. A System on a Chip (SOC) consistent with the present disclosure includes a host and a unified sensor interconnect. A unified sensor interconnect is to be coupled to the host and at least one device. In one or more implementations, the unified sensor interconnect includes a clock line, data line, ground line, and power source line. Further, the unified sensor interconnect is to enable interrupts from at least one of the host or the at least one device.
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公开(公告)号:US11334511B2
公开(公告)日:2022-05-17
申请号:US16655511
申请日:2019-10-17
Applicant: Intel Corporation
Inventor: Rajesh Bhaskar , Enrico Carrieri , Kenneth Foust , Janusz Jurski , Myron Loewen , Matthew A. Schnoor , Amit Kumar Srivastava , George Vergis
Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.
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5.
公开(公告)号:US20200050571A1
公开(公告)日:2020-02-13
申请号:US16655511
申请日:2019-10-17
Applicant: Intel Corporation
Inventor: Rajesh Bhaskar , Enrico Carrieri , Kenneth Foust , Janusz Jurski , Myron Loewen , Matthew A. Schnoor , Amit Kumar Srivastava , George Vergis
Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.
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