公开(公告)号：US20240006341A1

公开(公告)日：2024-01-04

申请号：US17857059

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L25/18 ,  H01L24/16 ,  H01L21/4803 ,  H01L2224/16225

Abstract: A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.

公开(公告)号：US20230120513A1

公开(公告)日：2023-04-20

申请号：US17971442

申请日：2022-10-21

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jenny Shio Yin ONG

IPC: H05K1/11

Abstract: Foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems. The fCAMM comprises a compression contact module having a plurality of contact means arranged in one or more arrays on its underside, first and second fold modules including multiple memory devices, and flexible interconnects coupling the compression contact module to the first and second fold modules. Under one assembled configuration, portions of printed circuit boards (PCBs) for the first and second fold modules are folded over portions of the compression contact module. Under another configuration, the first fold module is disposed above the second fold module, which is disposed above the compression contact module. In an assembly or system including a motherboard, a compression mount technology (CMT) connector or a land grid array (LGA) assembly is disposed between the motherboard and the compression contact module. Bolster plates are used to urge the compression contact module toward the motherboard.

公开(公告)号：US20220068833A1

公开(公告)日：2022-03-03

申请号：US17088618

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

公开(公告)号：US20240145420A1

公开(公告)日：2024-05-02

申请号：US17975654

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13188 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/30051 ,  H01L2224/3016 ,  H01L2224/32227 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83193 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/0133 ,  H01L2924/0543 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

公开(公告)号：US20240145365A1

公开(公告)日：2024-05-02

申请号：US18050519

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Kooi Chi OOI ,  Jackson Chung Peng KONG

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49833

Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.

公开(公告)号：US20230113084A1

公开(公告)日：2023-04-13

申请号：US17498001

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Kok Hou TEH ,  Kooi Chi OOI ,  Li Wern CHEW

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: The present disclosure generally relates to a printed circuit board assembly that may include a circuit board having a first surface and an opposing second surface. The printed circuit board assembly may also include a first interconnect barrel disposed in the circuit board. The first interconnect barrel may have a first length extending between the first surface and the second surface. The first interconnect barrel may include a first section, and may further include a second section spaced apart from the first section by a first gap having a first depth extending partially through the first length. The printed circuit board assembly may further include a first conductive trace coupled to the first section and a second conductive trace coupled to the second section at a first terminal.

公开(公告)号：US20190047559A1

公开(公告)日：2019-02-14

申请号：US16139805

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Naissa CONDE ,  Casey BARON ,  Shekoufeh QAWAMI ,  Kooi Chi OOI ,  Mengjie YU

IPC: B60W30/095 ,  B60W50/14 ,  G05D1/00

Abstract: Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.

公开(公告)号：US20190013301A1

公开(公告)日：2019-01-10

申请号：US15996093

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31

Abstract: Embodiments herein may include apparatuses, systems, and processes related to stacked dies that include recesses into which passive components, such as decoupling capacitors, may be included. Embodiments may include a first die with a first side and a second side opposite the first side, a second die with a first side coupled to the second side of the first die, a recess in the first side of the second die, wherein a portion of a passive component is located within the recess of the first side of the second die, and wherein the passive component is coupled with the first die, the second die, or both. Other embodiments may be described and/or claimed.

公开(公告)号：US20240136269A1

公开(公告)日：2024-04-25

申请号：US17968830

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

公开(公告)号：US20240071856A1

公开(公告)日：2024-02-29

申请号：US17895102

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/367 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L23/3736

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.