公开(公告)号：US20180188953A1

公开(公告)日：2018-07-05

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Zeshan A. CHISHTI ,  Muthukumar P. SWAMINATHAN ,  Alaa R. ALAMELDEEN ,  Kunal A. KHOCHARE ,  Jason A. GAYMAN

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3418

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US20210110862A1

公开(公告)日：2021-04-15

申请号：US17128963

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Akanksha MEHTA ,  Benjamin GRANIELLO ,  Rakan MADDAH ,  Philip HILLIER ,  Richard P. MANGOLD ,  Prashant S. DAMLE ,  Kunal A. KHOCHARE

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4076 ,  G11C15/04

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.