公开(公告)号：US20210056030A1

公开(公告)日：2021-02-25

申请号：US17092093

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20200026513A1

公开(公告)日：2020-01-23

申请号：US16585521

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Berkin AKIN ,  Alaa R. ALAMELDEEN

IPC: G06F9/30

Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

公开(公告)号：US20170277633A1

公开(公告)日：2017-09-28

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zhe WANG ,  Zeshan A. CHISHTI

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US20240078112A1

公开(公告)日：2024-03-07

申请号：US18388797

申请日：2023-11-10

Applicant: Intel Corporation

Inventor： Berkin AKIN ,  Alaa R. ALAMELDEEN

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30087

Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

公开(公告)号：US20190163628A1

公开(公告)日：2019-05-30

申请号：US16262691

申请日：2019-01-30

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN

IPC: G06F12/0804

Abstract: An apparatus is described. The apparatus includes memory control logic circuitry having circuity to a limit an amount of dirty data kept in a volatile level of a multi-level memory. The volatile level of the multi-level memory to act as a cache for a non-volatile, lower level of the multi-level memory. The amount of dirty data in the cache to be limited by the memory control logic circuitry to less than the capacity of the cache.

公开(公告)号：US20180188953A1

公开(公告)日：2018-07-05

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Zeshan A. CHISHTI ,  Muthukumar P. SWAMINATHAN ,  Alaa R. ALAMELDEEN ,  Kunal A. KHOCHARE ,  Jason A. GAYMAN

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3418

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US20200042343A1

公开(公告)日：2020-02-06

申请号：US16586859

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Andrew V. ANDERSON ,  Alaa R. ALAMELDEEN ,  Andrew M. RUDOFF

IPC: G06F9/455

Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

公开(公告)号：US20190179764A1

公开(公告)日：2019-06-13

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN ,  Lidia WARNES ,  Andy M. RUDOFF ,  Muthukumar P. SWAMINATHAN

IPC: G06F12/0891 ,  G06F12/0893 ,  G06F12/02

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US20190041952A1

公开(公告)日：2019-02-07

申请号：US16107215

申请日：2018-08-21

Applicant: INTEL CORPORATION

Inventor： Alaa R. ALAMELDEEN ,  Berkin AKIN

IPC: G06F1/32 ,  G06F13/42

Abstract: A device is configured to be in communication with one or more host cores via a first communication path. A first set of processing-in-memory (PIM) cores and a second set of PIM cores are configured to be in communication with a memory included in the device over a second communication path, wherein the first set of PIM cores have greater processing power than the second set of PIM cores, and wherein the second communication path has a greater bandwidth for data transfer than the first communication path. Code offloaded by the one or more host cores are executed in the first set of PIM cores and the second set of PIM cores.

公开(公告)号：US20180088853A1

公开(公告)日：2018-03-29

申请号：US15276677

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Jagadish B. KOTRA ,  Alaa R. ALAMELDEEN ,  Christopher B. WILKERSON ,  Jaewoong SIM

IPC: G06F3/06 ,  G06F12/0842

CPC classification number: G06F12/0842 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2212/311 ,  G06F2212/62

Abstract: A method is described. The method includes performing the following in a computing system having a multi-level system memory, the multi-level system memory having a first level and a second level: switching between utilization of the first level as a cache for the second level and separately addressable system memory depending on a state of the computing system.