公开(公告)号：US20180188953A1

公开(公告)日：2018-07-05

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Zeshan A. CHISHTI ,  Muthukumar P. SWAMINATHAN ,  Alaa R. ALAMELDEEN ,  Kunal A. KHOCHARE ,  Jason A. GAYMAN

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3418

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US20210011706A1

公开(公告)日：2021-01-14

申请号：US17031012

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Muthukumar P. SWAMINATHAN ,  Daniel K. OSAWA ,  Maciej PLUCINSKI

IPC: G06F8/65 ,  G06F21/44 ,  G06F3/06

Abstract: Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed.

公开(公告)号：US20170249250A1

公开(公告)日：2017-08-31

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Kai CHENG ,  Taarinya POLEPEDDI ,  Camille C. RAAD ,  David J. ZIMMERMAN ,  Muthukumar P. SWAMINATHAN ,  Dimitrios ZIAKAS ,  Mohan J. KUMAR ,  Bassam N. COURY ,  Glenn J. HINTON

IPC: G06F12/0811 ,  G11C11/406 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20190220406A1

公开(公告)日：2019-07-18

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Kai CHENG ,  Taarinya POLEPEDDI ,  Camille C. RAAD ,  David J. ZIMMERMAN ,  Muthukumar P. SWAMINATHAN ,  Dimitrios ZIAKAS ,  Mohan J. KUMAR ,  Bassam N. COURY ,  Glenn J. HINTON

IPC: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20190179764A1

公开(公告)日：2019-06-13

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN ,  Lidia WARNES ,  Andy M. RUDOFF ,  Muthukumar P. SWAMINATHAN

IPC: G06F12/0891 ,  G06F12/0893 ,  G06F12/02

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US20190018809A1

公开(公告)日：2019-01-17

申请号：US16046587

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Bill NALE ,  Raj K. RAMANUJAN ,  Muthukumar P. SWAMINATHAN ,  Tessil THOMAS ,  Taarinya POLEPEDDI

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F9/46 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/0802 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol