公开(公告)号：US20160300725A1

公开(公告)日：2016-10-13

申请号：US15036351

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising C12, Ar, and CH4.

Abstract translation: 本发明的实施例描述了具有高纵横比翅片的半导体器件和用于形成这种器件的方法。 根据实施例，半导体器件包括一个或多个嵌套散热片和一个或多个隔离鳍片。 根据实施例，通过硬掩模蚀刻工艺形成包括一个或多个隔离特征和一个或多个嵌套特征的图案化硬掩模。 第一衬底蚀刻工艺通过将硬掩模的嵌套和隔离特征的图案转移到衬底中形成第一深度来在衬底中形成隔离和嵌套的翅片。 使用第二蚀刻工艺将衬底蚀刻到第二深度。 根据本发明的实施例，第一蚀刻工艺利用包括HBr，O 2和CF 4的蚀刻化学品，第二蚀刻工艺利用包含C12，Ar和CH4的蚀刻化学品。

公开(公告)号：US20220344165A1

公开(公告)日：2022-10-27

申请号：US17860058

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US20200227266A1

公开(公告)日：2020-07-16

申请号：US16836432

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US20240120206A1

公开(公告)日：2024-04-11

申请号：US18531359

申请日：2023-12-06

Applicant: Intel Corporation

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US20210183658A1

公开(公告)日：2021-06-17

申请号：US17164230

申请日：2021-02-01

Applicant: Intel Corporation

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US20190131138A1

公开(公告)日：2019-05-02

申请号：US16234460

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Muralidhar S. AMBATI ,  Ritesh JHAVERI ,  Moosung KIM

IPC: H01L21/3065 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308

Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US20160343609A1

公开(公告)日：2016-11-24

申请号：US15224987

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Ritesh JHAVERI ,  Jeanne L. LUCE ,  Sang-Won PARK ,  Dennis G. HANKEN

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02345 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.