公开(公告)号：US20190181003A1

公开(公告)日：2019-06-13

申请号：US16324859

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jeanne L. LUCE ,  Ebony L. MAYS ,  Aravind S. KILLAMPALLI ,  Jay P. GUPTA

IPC: H01L21/02 ,  C23C16/56

CPC classification number: H01L21/02271 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02219 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02337 ,  H01L21/205 ,  H01L21/76828 ,  H01L21/76837 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5383

Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

公开(公告)号：US20240213250A1

公开(公告)日：2024-06-27

申请号：US18088547

申请日：2022-12-24

Applicant: INTEL CORPORATION

Inventor： Shao Ming KOH ,  Sudipto NASKAR ,  Leonard P. GULER ,  Patrick MORROW ,  Richard E. SCHENKER ,  Walid M. HAFEZ ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Jeanne L. LUCE ,  Dan S. LAVRIC ,  Jack T. KAVALIEROS ,  Matthew PRINCE ,  Lars LIEBMANN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.

公开(公告)号：US20200058761A1

公开(公告)日：2020-02-20

申请号：US16342865

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Byron HO ,  Michael L. HATTENDORF ,  Jeanne L. LUCE ,  Ebony L. MAYS ,  Erica J. THOMPSON

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/762

Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.

公开(公告)号：US20160343609A1

公开(公告)日：2016-11-24

申请号：US15224987

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Ritesh JHAVERI ,  Jeanne L. LUCE ,  Sang-Won PARK ,  Dennis G. HANKEN

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02345 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.