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公开(公告)号：US12243590B2
公开(公告)日：2025-03-04
申请号：US17528892
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Christian Mion , Pranav Kalavade , Rohit S. Shenoy , Xin Sun , Kristopher Gaewsky
Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.
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公开(公告)号：US11302405B2
公开(公告)日：2022-04-12
申请号：US16709749
申请日：2019-12-10
Applicant: Intel Corporation
Inventor： Sriram Natarajan , Shankar Natarajan , Yihua Zhang , Hinesh K. Shah , Rohit S. Shenoy , Arun Sitaram Athreya
Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.
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公开(公告)号：US20230154539A1
公开(公告)日：2023-05-18
申请号：US17528892
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Shantanu R. Rajwade , Christian Mion , Pranav Kalavade , Rohit S. Shenoy , Xin Sun , Kristopher Gaewsky
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3459 , G06F3/061 , G06F3/0659 , G06F3/0679 , G11C11/56
Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.
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Patent Agency Ranking
公开(公告)号：US20220101932A1
公开(公告)日：2022-03-31
申请号：US17032791
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Pranav Kalavade , Rohit S. Shenoy , Golnaz Karbasian
Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.
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公开(公告)号：US10242734B1
公开(公告)日：2019-03-26
申请号：US15720492
申请日：2017-09-29
Applicant: INTEL CORPORATION
Inventor： Ali Khakifirooz , Rohit S. Shenoy , Pranav Kalavade , Aliasgar S. Madraswala , Yogesh B. Wakchaure
Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.
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公开(公告)号：US12001280B2
公开(公告)日：2024-06-04
申请号：US17133995
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Krishna K. Parat , Ravi H. Motwani , Rohit S. Shenoy , Ali Khakifirooz
CPC classification number: G06F11/1068 , G11C11/5621 , G11C16/26 , G11C16/0483
Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.
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公开(公告)号：US11315644B2
公开(公告)日：2022-04-26
申请号：US17032791
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Pranav Kalavade , Rohit S. Shenoy , Golnaz Karbasian
Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.
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公开(公告)号：US10109361B1
公开(公告)日：2018-10-23
申请号：US15637481
申请日：2017-06-29
Applicant: Intel Corporation
Inventor： Ali Khakifirooz , Pranav Kalavade , Rohit S. Shenoy , Aliasgar S. Madraswala , Donia Sebastian , Xin Guo
Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.
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