公开(公告)号：US20180331184A1

公开(公告)日：2018-11-15

申请号：US15777553

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SEIYON KIM ,  JUN SUNG KANG

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

公开(公告)号：US20160260802A1

公开(公告)日：2016-09-08

申请号：US15155806

申请日：2016-05-16

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KELIN J. KUHN ,  SEIYON KIM ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20190279978A1

公开(公告)日：2019-09-12

申请号：US15754709

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO ,  SEIYON KIM

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In accordance with some embodiments, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in accordance with some embodiments, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.

公开(公告)号：US20150228772A1

公开(公告)日：2015-08-13

申请号：US14690615

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KELIN J. KUHN ,  SEIYON KIM ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract translation: 公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。 在一种这样的情况下，第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替，并且第二组牺牲散热片中的每一个凹进或以其它方式移除， 类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程，反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。