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    POWER MANAGEMENT FOR EXECUTION OF MACHINE LEARNING WORKLOADS
    1.
    发明公开
    POWER MANAGEMENT FOR EXECUTION OF MACHINE LEARNING WORKLOADS 审中-公开

    公开(公告)号：US20230273832A1

    公开(公告)日：2023-08-31

    申请号：US18133616

    申请日：2023-04-12

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Muhammad M. Khellah ,  Linda Zeng ,  Mohamed Elmalaki

    IPC: G06F9/50 ,  G06F1/3228 ,  G06F1/3296

    CPC classification number: G06F9/505 ,  G06F1/3228 ,  G06F1/3296

    Abstract: A system for autonomous and proactive power management for energy efficient execution of machine learning workloads may include an apparatus such as system-on-chip (SoC) comprising an accelerator configurable to load and execute a neural network and circuitry to receive a profile of the neural network. The profile may be received from a compiler and include information regarding a plurality of layers of the neural network. Responsive to the profile and the information regarding the plurality of layers, circuitry may adjust, using a local power management unit (PMU) included the apparatus, a power level to the accelerator while the accelerator executes the neural network. The power level adjustment may be based on whether the particular layer is a compute-intensive layer or a memory-intensive layer.

    Techniques for multi-read and multi-write of memory circuit
    2.
    发明授权
    Techniques for multi-read and multi-write of memory circuit 有权

    公开(公告)号：US11176994B2

    公开(公告)日：2021-11-16

    申请号：US17001432

    申请日：2020-08-24

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    Pre-synaptic learning using delayed causal updates
    3.
    发明授权
    Pre-synaptic learning using delayed causal updates 有权

    公开(公告)号：US10748060B2

    公开(公告)日：2020-08-18

    申请号：US15294666

    申请日：2016-10-14

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N20/00 ,  G06N3/04 ,  G06N3/063

    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

    POST SYNAPTIC POTENTIAL-BASED LEARNING RULE
    4.
    发明申请
    POST SYNAPTIC POTENTIAL-BASED LEARNING RULE 审中-公开

    公开(公告)号：US20180322384A1

    公开(公告)日：2018-11-08

    申请号：US15584510

    申请日：2017-05-02

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Somnath Paul ,  Sadique Ul Ameen Sheik ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04

    Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

    Techniques for resilient communication
    6.
    发明授权
    Techniques for resilient communication 有权
    弹性沟通技巧

    公开(公告)号：US08990662B2

    公开(公告)日：2015-03-24

    申请号：US13631937

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

    IPC: H03M13/00 ,  G06F11/14

    CPC classification number: G06F11/1443 ,  H04L1/20 ,  H04L1/242

    Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

    Abstract translation: 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得​​输出级发送通过链路发送的数据的副本。

    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT
    9.
    发明申请
    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT 有权

    公开(公告)号：US20210043251A1

    公开(公告)日：2021-02-11

    申请号：US17001432

    申请日：2020-08-24

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    Techniques for multi-read and multi-write of memory circuit
    10.
    发明授权
    Techniques for multi-read and multi-write of memory circuit 有权

    公开(公告)号：US10755771B2

    公开(公告)日：2020-08-25

    申请号：US16226385

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

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