公开(公告)号：US20160225665A1

公开(公告)日：2016-08-04

申请号：US15096609

申请日：2016-04-12

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Abstract translation: 介电层及其形成方法。 限定在电介质层中的开口和沉积在开口内的电线，其中电线包括由护套材料围绕的芯材料，其中护套材料表现出第一电阻率ρ1，并且芯材料表现出第二电阻率ρ2且ρ2较小 比ρ1。

公开(公告)号：US20210020502A1

公开(公告)日：2021-01-21

申请号：US17061062

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20180350672A1

公开(公告)日：2018-12-06

申请号：US16005175

申请日：2018-06-11

Applicant: INTEL CORPORATION

Inventor： YURIY V. SHUSTERMAN ,  FLAVIO GRIGGIO ,  TEJASWI K. INDUKURI ,  RUTH A. BRAIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L23/31 ,  H01L21/3213 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20180240969A1

公开(公告)日：2018-08-23

申请号：US15753478

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： MARK L. DOCZY ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  KAAN OGUZ ,  KEVIN P. O'BRIEN ,  SATYARTH SURI ,  TEJASWI K. INDUKURI

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20170372950A1

公开(公告)日：2017-12-28

申请号：US15631701

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20170338148A1

公开(公告)日：2017-11-23

申请号：US15528425

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： YURIY V. SHUSTERMAN ,  FLAVIO GRIGGIO ,  TEJASWI K. INDUKURI ,  RUTH A. BRAIN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.