公开(公告)号：US20200006625A1

公开(公告)日：2020-01-02

申请号：US16021425

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： KAAN OGUZ ,  TANAY GOSAVI ,  SASIKANTH MANIPATRUNI ,  CHIA-CHING LIN ,  GARY ALLEN

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30

Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.

公开(公告)号：US20170092846A1

公开(公告)日：2017-03-30

申请号：US15126682

申请日：2014-07-07

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20160359101A1

公开(公告)日：2016-12-08

申请号：US15117605

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： CHARLES C. KUO ,  KAAN OGUZ ,  BRIAN S. DOYLE ,  MARK L. DOCZY ,  DAVID L. KENCKE ,  SATYARTH SURI ,  ROBERT S. CHAU

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract translation: 公开了用于制造具有点接触自由磁性层的自对准自旋转移转矩存储器（STTM）装置的技术。 在一些实施例中，所公开的STTM装置包括覆盖导电硬掩模层的侧壁的第一介电间隔物，其被图案化以提供用于STTM自由磁性层的电子接触。 硬掩模接触可以比自由磁性层更窄。 第一介电间隔物可用于图案化STTM的固定磁性层。 在一些实施例中，STTM还包括覆盖其自由磁性层的侧壁的任选的第二电介质间隔物。 第二电介质间隔物可以用于图案化STTM的固定磁性层，并且可以至少部分地用于保护自由磁性层的侧壁在这种图案化期间重新沉积蚀刻副产物，从而防止固定磁性层 和自由磁性层。

公开(公告)号：US20190109281A1

公开(公告)日：2019-04-11

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  CHARLES C. KUO ,  MARK L. DOCZY ,  SATYARTH SURI ,  DAVID L. KENCKE ,  ROBERT S. CHAU ,  ROKSANA GOLIZADEH MOJARAD

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2213/52 ,  H01L27/222 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20210296040A1

公开(公告)日：2021-09-23

申请号：US16329309

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： KAAN OGUZ ,  KEVIN P. O'BRIEN ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  MARK L. DOCZY

IPC: H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

公开(公告)号：US20180240969A1

公开(公告)日：2018-08-23

申请号：US15753478

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： MARK L. DOCZY ,  BRIAN S. DOYLE ,  CHARLES C. KUO ,  KAAN OGUZ ,  KEVIN P. O'BRIEN ,  SATYARTH SURI ,  TEJASWI K. INDUKURI

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20160126452A1

公开(公告)日：2016-05-05

申请号：US14992601

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： CHARLES C. KUO ,  BRIAN S. DOYLE ,  Arijit Raychowdhury ,  ROKSANA GOLIZADEH MOJARAD ,  KAAN OGUZ

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.

Abstract translation: 公开了通过在其中实现附加铁磁层来增强垂直磁隧道结（MTJ）的性能的技术。 附加铁磁层可以例如在垂直MTJ的固定铁磁层或自由铁磁层中或以其它方式实现。 在一些实施例中，附加铁磁层用非磁性间隔件实现，其中可以调整附加铁磁层和/或间隔物的厚度以使垂直MTJ的平行和反平行状态之间的能量势垒充分平衡。 在一些实施例中，附加铁磁层被配置为使得其磁化强度与固定铁磁层的磁化强度相反。

公开(公告)号：US20190386014A1

公开(公告)日：2019-12-19

申请号：US16465044

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  KAAN OGUZ ,  RICKY J. TSENG ,  KEVIN P. O'BRIEN

IPC: H01L27/1159 ,  G11C5/06 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

公开(公告)号：US20190049514A1

公开(公告)日：2019-02-14

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN P. O'BRIEN ,  KAAN OGUZ ,  CHRISTOPHER J. WIEGAND ,  MARK L. DOCZY ,  BRIAN S. DOYLE ,  MD TOFIZUR RAHMAN ,  OLEG GOLONZKA ,  TAHIR GHANI

IPC: G01R31/28 ,  G01R31/315 ,  H01L21/66 ,  G01R33/09 ,  H01L43/12

CPC classification number: G01R31/2831 ,  G01N24/10 ,  G01R31/315 ,  G01R33/098 ,  G01R33/60 ,  G01R35/00 ,  H01L22/14 ,  H01L43/12

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

公开(公告)号：US20160351238A1

公开(公告)日：2016-12-01

申请号：US15116457

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： BRIAN S. DOYLE ,  DAVID L. KENCKE ,  KAAN OGUZ ,  MARK L. DOCZY ,  SATYARTH SURI ,  ROBERT S. CHAU ,  CHARLES C. KUO ,  ROKSANA GOLIZADEH MOJARAD

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.

Abstract translation: 公开了用于形成具有环形接触的自旋转移力矩存储器（STTM）元件以减少临界电流要求的技术。 该技术降低给定磁性隧道结（MTJ）的临界电流要求，因为环形接触可以减小接触尺寸并增加局部电流密度，从而减少切换MTJ自由磁性层方向所需的电流。 在一些情况下，环形触点围绕防止电流通过的绝缘体层的至少一部分。 在这种情况下，电流流过环形触点并且在绝缘体层周围流动，以在流过自由磁性层之前增加局部电流密度。 绝缘体层可以包括介电材料，并且在一些情况下，是隧道材料，例如氧化镁（MgO）。 在某些情况下，对于给定的MTJ，实现至少10％的临界电流降低。