公开(公告)号：US20170098709A1

公开(公告)日：2017-04-06

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： NEVILLE L. DIAS ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  ROMAN W. OLAC-VAW ,  HSU-YU CHANG ,  TING CHANG ,  RAHUL RAMASWAMY ,  PEI-CHI LIU

IPC: H01L29/78 ,  H01L29/10 ,  H03D7/14 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

Abstract: An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.

公开(公告)号：US20160049418A1

公开(公告)日：2016-02-18

申请号：US14779938

申请日：2013-06-25

Applicant: INTEL CORPORATION

Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

Abstract translation: 描述了具有隔离电荷位置的存储单元和制造具有隔离电荷位点的存储单元的方法。 在一个示例中，非易失性电荷陷阱存储器件包括具有沟道区，源极区和漏极区的衬底。 栅极堆叠设置在衬底上方，在沟道区域上方。 栅堆叠包括设置在沟道区上方的隧道介电层，第一电荷俘获区和第二电荷俘获区。 这些区域设置在隧道介电层上方并分开一段距离。 栅堆叠还包括设置在隧道介电层上方和第一电荷俘获区与第二电荷俘获区之间的隔离电介质层。 栅电介质层设置在第一电荷捕获区，第二电荷捕获区和隔离电介质层的上方。 栅极电极设置在栅极电介质层的上方。

公开(公告)号：US20180218977A1

公开(公告)日：2018-08-02

申请号：US15935838

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

IPC: H01L23/525 ,  G11C17/14 ,  H01L27/112 ,  H01L27/102 ,  H01L23/62 ,  G11C17/16

CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

公开(公告)号：US20160351498A1

公开(公告)日：2016-12-01

申请号：US15117621

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

IPC: H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

Abstract translation: 公开了用于有效实现包括非易失性和易失性存储器的可编程存储器阵列电路架构的技术和电路。 存储器电路采用包括1T位单元的阵列的反熔断器方案，其中每个位单元有效地包含一个栅极或类似晶体管的器件，其为该位单元提供反熔丝元件和选择器器件。 特别地，位单元器件具有不对称的基于沟槽的源极/漏极触点，使得一个触点与间隔物和栅极金属结合形成电容器，而另一个触点与掺杂扩散区域和栅极金属结合形成二极管。 电容器用作位单元的反熔断元件，并且可以通过分解间隔件来编程。 该二极管有效地提供肖特基结，其作为选择器装置，其可以消除共享相同位线/字线的位单元的程序和读取干扰。