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公开(公告)号：US10963031B2
公开(公告)日：2021-03-30
申请号：US15906960
申请日：2018-02-27
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
IPC: G06F1/3206 , H04B3/54 , H04B3/56 , G06F1/3209 , G06F1/26 , H04H20/38 , H04L12/863
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US09933829B2
公开(公告)日：2018-04-03
申请号：US15258803
申请日：2016-09-07
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US09268393B2
公开(公告)日：2016-02-23
申请号：US13997295
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
CPC classification number: G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。
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公开(公告)号：US10037075B2
公开(公告)日：2018-07-31
申请号：US15089489
申请日：2016-04-02
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman
CPC classification number: G06F1/3296 , G06F1/26 , G06F1/263 , G06F1/305 , H02J7/00 , H02M3/04 , Y02D10/172
Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10564709B2
公开(公告)日：2020-02-18
申请号：US16049779
申请日：2018-07-30
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman
IPC: G06F1/3296 , G06F1/26 , G06F1/30 , H02M3/04 , H02J7/00
Abstract: Voltage regulation techniques for electronic devices are described. In one embodiment, for example, an apparatus may comprise an electronic element comprising one or more integrated circuits, a voltage regulator to regulate an input voltage of the electronic element, the voltage regulator to source an output current comprising at least a portion of an input current of the electronic element, the voltage regulator to operate in a current-limiting mode to limit the output current when the input current exceeds a threshold current, and a capacitor bank comprising one or more capacitors, the capacitor bank to source a supplemental current to supplement the output current of the voltage regulator when the voltage regulator operates in the current-limiting mode. Other embodiments are described and claimed.
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公开(公告)号：US20160380675A1
公开(公告)日：2016-12-29
申请号：US15258803
申请日：2016-09-07
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
IPC: H04B3/54 , H04H20/38 , H04L12/863
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US09461709B2
公开(公告)日：2016-10-04
申请号：US14319485
申请日：2014-06-30
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
Abstract translation: 服务器系统包括公用电源总线，用于通过公共电源总线提供直流（DC）电力的电源，至少一个节点，其包括处理器以通过公共电源总线接收DC电力;发射机电容耦合到 公共电源总线，用于通过公共电源总线从电源传输电力信息信号;以及至少一个接收器，电容耦合到公共电力总线，以接收由发射机发送的电力信息信号，并将接收到的功率信息信号提供给 该至少一个节点。 分别耦合在公共电源总线与电源和至少一个节点中的每一个的多个缓冲器为高频和低频电流提供路径间隔。
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公开(公告)号：US20180188790A1
公开(公告)日：2018-07-05
申请号：US15906960
申请日：2018-02-27
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US20150381237A1
公开(公告)日：2015-12-31
申请号：US14319485
申请日：2014-06-30
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
Abstract translation: 服务器系统包括公用电源总线，用于通过公共电源总线提供直流（DC）电力的电源，至少一个节点，其包括处理器以通过公共电源总线接收DC电力;发射机电容耦合到 公共电源总线，用于通过公共电源总线从电源传输电力信息信号;以及至少一个接收器，电容耦合到公共电力总线，以接收由发射机发送的电力信息信号，并将接收到的功率信息信号提供给 该至少一个节点。 分别耦合在公共电源总线与电源和至少一个节点中的每一个的多个缓冲器为高频和低频电流提供路径间隔。
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