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公开(公告)号：US20170359226A1
公开(公告)日：2017-12-14
申请号：US15181041
申请日：2016-06-13
Applicant: INTEL CORPORATION
Inventor： Devadatta Bodas , Justin J. Song , Muralidhar Rajappa , Andy Hoffman
CPC classification number: H04L41/142 , H04L69/22 , H04L69/329
Abstract: A zombie server can be detected. Detecting a zombie server can include receiving, at a server, network traffic and calculating a percentage of the network traffic as being productivity software layer 7 protocols every first time interval. Detecting a zombie server can also include marking the server as a zombie server based on the percentage every second time interval and processing the network traffic at the server to perform a number of actions by the productivity software.
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2.发明申请公开(公告)号：US20170285702A1
公开(公告)日：2017-10-05
申请号：US15084374
申请日：2016-03-29
Applicant: Intel Corporation
Inventor： Justin J. Song , Devadatta V. Bodas , Muralidhar Rajappa , Brian J. Griffith , Andy Hoffman , Gopal R. Mundada
IPC: G06F1/26
Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.
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公开(公告)号：US11435809B2
公开(公告)日：2022-09-06
申请号：US17306786
申请日：2021-05-03
Applicant: Intel Corporation
Inventor： Devadatta V. Bodas , Muralidhar Rajappa , Justin J. Song , Andy Hoffman
IPC: G06F1/32 , G06F1/324 , G06F1/3228
Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.
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公开(公告)号：US10904127B2
公开(公告)日：2021-01-26
申请号：US15181001
申请日：2016-06-13
Applicant: INTEL CORPORATION
Inventor： Devadatta Bodas , Justin J. Song , Muralidhar Rajappa , Andy Hoffman
Abstract: A zombie server can be detected. Detecting a zombie server can include labeling a plurality of processes as utility software, calculating a utilization of utility software on the plurality of processes executed in one or more processing resources during an interval of time, and calculating a server utilization of the one or more processing resources during the interval of time. Detecting the zombie server can also include determining whether a difference between the utilization of utility software and the server utilization is greater than a threshold, and identifying a server that hosts the processing resource as a zombie server based on a determination that the difference is smaller than the threshold.
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公开(公告)号：US10404676B2
公开(公告)日：2019-09-03
申请号：US15084377
申请日：2016-03-29
Applicant: Intel Corporation
Inventor： Justin J. Song , Devadatta V. Bodas , Muralidhar Rajappa , Andy Hoffman , Mariusz Oriol , Gopal R. Mundada
IPC: H04L29/06 , G06F1/3203 , G06F21/55 , H04L12/24
Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.
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Patent Agency Ranking
公开(公告)号：US10261559B2
公开(公告)日：2019-04-16
申请号：US15040160
申请日：2016-02-10
Applicant: Intel Corporation
Inventor： Justin J. Song , Qian Diao
IPC: G06F1/28 , G06F1/00 , G06F1/32 , G06F1/3203
Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.
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公开(公告)号：US20160380675A1
公开(公告)日：2016-12-29
申请号：US15258803
申请日：2016-09-07
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
IPC: H04B3/54 , H04H20/38 , H04L12/863
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
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公开(公告)号：US09461709B2
公开(公告)日：2016-10-04
申请号：US14319485
申请日：2014-06-30
Applicant: INTEL CORPORATION
Inventor： Brian J. Griffith , Viktor D. Vogman , Justin J. Song
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3209 , H04B3/546 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04B2203/5495 , H04H20/38 , H04L47/50 , Y04S40/146
Abstract: A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a processor to receive the DC power through the common power bus, a transmitter capacitive coupled to the common power bus to transmit a power information signal from the power supply through the common power bus, and at least one receiver capacitive coupled to the common power bus to receive the power information signal transmitted by the transmitter and to provide the received power information signal to the at least one node. A plurality of buffers respectively coupled between the common power bus and each of the power supply and the at least one node provide path separation for high frequency and low frequency currents.
Abstract translation: 服务器系统包括公用电源总线，用于通过公共电源总线提供直流（DC）电力的电源，至少一个节点，其包括处理器以通过公共电源总线接收DC电力;发射机电容耦合到 公共电源总线，用于通过公共电源总线从电源传输电力信息信号;以及至少一个接收器，电容耦合到公共电力总线，以接收由发射机发送的电力信息信号，并将接收到的功率信息信号提供给 该至少一个节点。 分别耦合在公共电源总线与电源和至少一个节点中的每一个的多个缓冲器为高频和低频电流提供路径间隔。
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公开(公告)号：US20160188379A1
公开(公告)日：2016-06-30
申请号：US14582979
申请日：2014-12-24
Applicant: Intel Corporation
Inventor： Muralidhar Rajappa , Andy Hoffman , Devadatta V. Bodas , Justin J. Song , James W. Alexander
IPC: G06F9/52
CPC classification number: G06F9/52 , G06F9/5083 , G06F9/5094 , G06F9/522 , G06F2209/5013 , Y02D10/22
Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.
Abstract translation: 一种用于分布式计算的系统和方法，包括在计算节点上执行分布式计算任务。 调整在计算节点上执行的作业的并行任务的速度以提高作业的性能或降低作业的功率消耗，或者两者，其中调整基于并行任务的相应速度的不平衡。
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公开(公告)号：US20160187906A1
公开(公告)日：2016-06-30
申请号：US14582985
申请日：2014-12-24
Applicant: INTEL CORPORATION
Inventor： Devadatta V. Bodas , Muralidhar Rajappa , Justin J. Song , Andy Hoffman , Michael K. Patterson
CPC classification number: G05F1/66 , G05B15/02 , G06F1/3203 , G06F1/329
Abstract: A system and method for computing at a facility having systems of multiple compute nodes to execute jobs of computing. Power consumption of the facility is managed to within a power band. The power consumption may be adjusted by implementing (e.g., by a power balloon) activities having little or no computational output.
Abstract translation: 一种用于在具有多个计算节点的系统的设施上进行计算以执行计算的作业的系统和方法。 设备的功耗被控制在功率范围内。 可以通过实施具有很少或没有计算输出的（例如，通过动力气球）活动来调节功率消耗。
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