公开(公告)号：US20220374320A1

公开(公告)日：2022-11-24

申请号：US17854449

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Chuan SONG ,  Mohan J. KUMAR ,  Feng JIANG ,  Yang ZHANG ,  Chong HAN

IPC: G06F11/20

Abstract: Examples described herein relate to execution of multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process. In some examples, the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors. In some examples, failure or timeout of the first RAS process comprises failure of the second RAS process to receive an operating status signal from the first RAS process.

公开(公告)号：US20180024854A1

公开(公告)日：2018-01-25

申请号：US15552407

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Wei WANG ,  Yaozu DONG ,  Yang ZHANG

IPC: G06F9/455 ,  G06F9/50 ,  G06F12/1027

CPC classification number: G06F9/45558 ,  G06F9/5088 ,  G06F12/1027 ,  G06F2009/45566 ,  G06F2009/4557 ,  G06F2009/45575 ,  G06F2009/45583 ,  G06F2212/657

Abstract: Technologies for virtual machine migration are disclosed. A plurality of virtual machines may be established on a source node at varying tiers of quality-of-service. The source node may identify a set of virtual machines from the plurality of virtual machines having a lower or lowest tier of quality-of-service. Additionally, the source node may perform a pseudo-migration for each of the virtual machines of the identified set to determine a dynamic working set for each corresponding virtual machine. The source node may select a virtual machine for migration based on the dynamic working set. The pseudo migration may include emulation of a pre-copy phase of a corresponding live migration to identify the number of dirty memory pages likely to result during the corresponding live migration of the corresponding virtual machine.

公开(公告)号：US20250113595A1

公开(公告)日：2025-04-03

申请号：US18374607

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure. The PN boundary is offset from a central location between the first fin structure or vertical arrangement of horizontal nanowires and the second fin structure or vertical arrangement of horizontal nanowires.

公开(公告)号：US20250107175A1

公开(公告)日：2025-03-27

申请号：US18372506

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region. Ends of the gate line shared between the NMOS region and the PMOS region are offset from ends of the trench contact structure shared between the NMOS region and the PMOS region.

公开(公告)号：US20250113547A1

公开(公告)日：2025-04-03

申请号：US18375064

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tao CHU ,  Chiao-Ti HUANG ,  Guowei XU ,  Robin CHAO ,  Feng ZHANG ,  Yue ZHONG ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Kevin P. O’BRIEN ,  Uygar E. AVCI ,  Carl H. NAYLOR ,  Mahmut Sami KAVRIK ,  Andrey VYATSKIKH ,  Rachel STEINHARDT ,  Chelsey DOROW ,  Kirby MAXEY

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

公开(公告)号：US20250112120A1

公开(公告)日：2025-04-03

申请号：US18375084

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Conor P. PULS ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

公开(公告)号：US20250098260A1

公开(公告)日：2025-03-20

申请号：US18370287

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Guowei XU ,  Feng ZHANG ,  Chiao-Ti HUANG ,  Robin CHAO ,  Tao CHU ,  Chung-Hsun LIN ,  Oleg GOLONZKA ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Anand S. MURTHY

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

公开(公告)号：US20250113559A1

公开(公告)日：2025-04-03

申请号：US18374600

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Guowei XU ,  Chiao-Ti HUANG ,  Feng ZHANG ,  Robin CHAO ,  Tao CHU ,  Anand S. MURTHY ,  Ting-Hsiang HUNG ,  Chung-Hsun LIN ,  Oleg GOLONZKA ,  Yang ZHANG ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

公开(公告)号：US20180246751A1

公开(公告)日：2018-08-30

申请号：US15756470

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Yao Zu DONG ,  Yang ZHANG

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/48 ,  G06F9/4856 ,  G06F9/505 ,  G06F2009/4557

Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a first VM from among a plurality of VM hosted by a source node for a first live migration to a destination node based on determined working set patterns and one or more policies.