公开(公告)号：US11562181B2

公开(公告)日：2023-01-24

申请号：US16948304

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Yen-Kuang Chen ,  Shao-Wen Yang ,  Ibrahima J. Ndiour ,  Yiting Liao ,  Vallabhajosyula S. Somayazulu ,  Omesh Tickoo ,  Srenivas Varadarajan

IPC: G06K9/62 ,  H04L9/06 ,  G06F21/64 ,  G06F21/53 ,  G06N5/02 ,  G06N3/04 ,  G06F21/45 ,  H04L9/32 ,  H04W4/70 ,  G06F21/44 ,  G06F16/538 ,  G06F16/535 ,  G06F16/54 ,  G06F21/62 ,  G06F9/50 ,  G06N3/063 ,  G06V10/20 ,  G06V10/40 ,  G06V10/75 ,  G06V10/44 ,  G06V20/00 ,  G06V40/20 ,  G06V40/16 ,  G06F9/48 ,  H04L67/51 ,  G06T7/11 ,  G06V10/96 ,  G06V30/262 ,  G06K15/02 ,  G06N3/08 ,  H04L67/12 ,  H04N19/80 ,  G06F16/951 ,  H04N19/46 ,  G06T7/70 ,  H04W12/02 ,  H04L9/00 ,  H04N19/12 ,  H04N19/124 ,  H04N19/167 ,  H04N19/172 ,  H04N19/176 ,  H04N19/44 ,  H04N19/48 ,  H04N19/513 ,  G06V30/194 ,  G06T7/20 ,  H04N19/42 ,  H04N19/625 ,  H04N19/63 ,  G06T7/223 ,  H04L67/10

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store visual data associated with a visual representation captured by one or more sensors. The processor is to: obtain the visual data associated with the visual representation captured by the one or more sensors, wherein the visual data comprises uncompressed visual data or compressed visual data; process the visual data using a convolutional neural network (CNN), wherein the CNN comprises a plurality of layers, wherein the plurality of layers comprises a plurality of filters, and wherein the plurality of filters comprises one or more pixel-domain filters to perform processing associated with uncompressed data and one or more compressed-domain filters to perform processing associated with compressed data; and classify the visual data based on an output of the CNN.

公开(公告)号：US11166041B2

公开(公告)日：2021-11-02

申请号：US16457802

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Yiting Liao ,  Yen-Kuang Chen ,  Shao-Wen Yang ,  Vallabhajosyula S. Somayazulu ,  Srenivas Varadarajan ,  Omesh Tickoo ,  Ibrahima J. Ndiour

IPC: H04N19/52 ,  G06K9/32 ,  G06K9/62 ,  G06N3/04 ,  H04N19/172 ,  H04N19/523

Abstract: In one embodiment, an apparatus comprises processing circuitry to: receive, via a communication interface, a compressed video stream captured by a camera, wherein the compressed video stream comprises: a first compressed frame; and a second compressed frame, wherein the second compressed frame is compressed based at least in part on the first compressed frame, and wherein the second compressed frame comprises a plurality of motion vectors; decompress the first compressed frame into a first decompressed frame; perform pixel-domain object detection to detect an object at a first position in the first decompressed frame; and perform compressed-domain object detection to detect the object at a second position in the second compressed frame, wherein the object is detected at the second position in the second compressed frame based on: the first position of the object in the first decompressed frame; and the plurality of motion vectors from the second compressed frame.

公开(公告)号：US20210209473A1

公开(公告)日：2021-07-08

申请号：US17212747

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Julio Cesar Zamora Esquivel ,  Jesus Adan Cruz Vargas ,  Nadine L. Dabby ,  Anthony Rhodes ,  Omesh Tickoo ,  Narayan Sundararajan ,  Lama Nachman

IPC: G06N3/08 ,  G06N3/04

Abstract: The present disclosure provides a machine learning model where each activation node within the model has an adaptive activation function defined in terms of an input and a hyperparameter of the model. Accordingly, each activation node can have a separate of distinct activation function, based on the adaptive activation function where the hyperparameter for each activation node is trained during overall training of the model. Furthermore, the present disclosure provides that a set of adaptive activation functions can be provided for each activation node such that a spike train of activations can be generated.

公开(公告)号：US20200326667A1

公开(公告)日：2020-10-15

申请号：US16911100

申请日：2020-06-24

Applicant: Intel Corporation

Inventor： Nilesh Ahuja ,  Ignacio J. Alvarez ,  Ranganath Krishnan ,  Ibrahima J. Ndiour ,  Mahesh Subedar ,  Omesh Tickoo

IPC: G05B13/02 ,  G06N3/08 ,  G06N7/00 ,  G06N5/04 ,  G06K9/62

Abstract: Techniques are disclosed for using neural network architectures to estimate predictive uncertainty measures, which quantify how much trust should be placed in the deep neural network (DNN) results. The techniques include measuring reliable uncertainty scores for a neural network, which are widely used in perception and decision-making tasks in automated driving. The uncertainty measurements are made with respect to both model uncertainty and data uncertainty, and may implement Bayesian neural networks or other types of neural networks.

公开(公告)号：US20200310532A1

公开(公告)日：2020-10-01

申请号：US16901412

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Ravishankar R. Iyer ,  Omesh Tickoo ,  Glen J. Anderson

IPC: G06F3/01 ,  G06K9/00 ,  G06F3/0484 ,  G06K9/62 ,  G06K9/46 ,  G02B27/01

Abstract: Generally discussed herein are systems and apparatuses for gesture-based augmented reality. Also discussed herein are methods of using the systems and apparatuses. According to an example a method may include detecting, in image data, an object and a gesture, in response to detecting the object in the image data, providing data indicative of the detected object, in response to detecting the gesture in the image data, providing data indicative of the detected gesture, and modifying the image data using the data indicative of the detected object and the data indicative of the detected gesture.

公开(公告)号：US20200250003A1

公开(公告)日：2020-08-06

申请号：US16652038

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Yen-Kuang Chen ,  Ragaad Mohammed Irsehid Altarawneh ,  Juan Pablo Munoz Chiabrando ,  Siew Wen Chin ,  Kushal Datta ,  Subramanya R. Dulloor ,  Julio C. Zamora Esquivel ,  Omar Ulises Florez Choque ,  Vishakha Gupta ,  Scott D. Hahn ,  Rameshkumar Illikkal ,  Nilesh Kumar Jain ,  Siti Khairuni Amalina Kamarol ,  Anil S. Keshavamurthy ,  Heng Kar Lau ,  Jonathan A. Lefman ,  Yiting Liao ,  Michael G. Millsap ,  Ibrahima J. Ndiour ,  Luis Carlos Maria Remis ,  Addicam V. Sanjay ,  Usman Sarwar ,  Eve M. Schooler ,  Ned M. Smith ,  Vallabhajosyula S. Somayazulu ,  Christina R. Strong ,  Omesh Tickoo ,  Srenivas Varadarajan ,  Jesús A. Cruz Vargas ,  Hassnaa Moustafa ,  Arun Raghunath ,  Katalin Klara Bartfai-Walcott ,  Maruti Gupta Hyde ,  Deepak S. Vembar ,  Jessica McCarthy

IPC: G06F9/50 ,  G06K9/00 ,  G06N3/04 ,  G06N3/063

Abstract: In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.

公开(公告)号：US10582196B2

公开(公告)日：2020-03-03

申请号：US15640198

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Javier Perez-Ramirez ,  Srenivas Varadarajan ,  Yiting Liao ,  Vallabhajosyula S. Somayazulu ,  Omesh Tickoo ,  Ibrahima J. Ndiour

IPC: H04N19/109 ,  H04N19/167 ,  H04N19/172 ,  H04N19/126

Abstract: An example apparatus for encoding video frames includes a receiver to receive events from a dynamic vision sensor and a video frame from an image sensor. The apparatus also includes a heat map generator to generate a heat map based on the received events. The apparatus further includes a region of interest (ROI) map generator generate a ROI map based on the heat map. The apparatus includes a parameter adjuster to adjust an encoding parameter based on the ROI map. The apparatus also further includes a video encoder to encode the video frame using the adjusted parameter.

公开(公告)号：US10552550B2

公开(公告)日：2020-02-04

申请号：US14866897

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Glen J. Anderson ,  Kevin W. Bross ,  Shawn S. Mceuen ,  Mark R. Francis ,  Yevgeniy Y. Yarmosh ,  Blanka Vlasak ,  Gregory A. Peek ,  Therese E. Dugan ,  Cory A. Harris ,  Ravishankar Iyer ,  Omesh Tickoo ,  David I. Poisner

IPC: G06F17/50 ,  G06F8/30

Abstract: Technologies for physical programming include a model compute system to determine one or more physical blocks assembled in a constructed model. The model compute system determines rules associated with the one or more physical blocks in which at least one rule defines a behavior of the constructed model and determines a program stack for execution by the model compute system based on the rules associated with the one or more physical blocks.

公开(公告)号：US10229324B2

公开(公告)日：2019-03-12

申请号：US14998322

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Myung Hwangbo ,  Krishna Kumar Singh ,  Teahyung Lee ,  Omesh Tickoo

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/62

Abstract: An apparatus for video summarization using semantic information is described herein. The apparatus includes a controller, a scoring mechanism, and a summarizer. The controller is to segment an incoming video stream into a plurality of activity segments, wherein each frame is associated with an activity. The scoring mechanism is to calculate a score for each frame of each activity, wherein the score is based on a plurality of objects in each frame. The summarizer is to summarize the activity segments based on the score for each frame.

公开(公告)号：US20190044536A1

公开(公告)日：2019-02-07

申请号：US16022631

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Omesh Tickoo ,  Wei WU

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/611

Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.