公开(公告)号：US20130228904A1

公开(公告)日：2013-09-05

申请号：US13673318

申请日：2012-11-09

Applicant: INTEL MOBILE COMMUNICATIONS GMBH

Inventor： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Brandl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract translation: 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US08779563B2

公开(公告)日：2014-07-15

申请号：US13673318

申请日：2012-11-09

Applicant: Intel Mobile Communications GmbH

Inventor： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Brandl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC: H01L23/552 ,  H01L23/42

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract translation: 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。