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1.发明授权Chip arrangement with a recessed chip housing region and a method for manufacturing the same 有权具有凹陷芯片壳体区域的芯片布置及其制造方法公开(公告)号：US09111947B2
公开(公告)日：2015-08-18
申请号：US13909158
申请日：2013-06-04
发明人： David O'Sullivan , Thorsten Meyer
CPC分类号： H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3157 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2924/12042 , H01L2924/181 , H01L2924/1815 , H01L2924/19104 , H01L2924/00
摘要： A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.
摘要翻译： 芯片布置可以包括：半导体芯片; 至少部分地封装半导体芯片的封装结构，所述封装结构具有第一侧和与所述第一侧相对的第二侧，所述封装结构包括在所述封装结构的第一侧上的凹部，所述凹部具有位于 一级; 以及至少一个电连接器，其设置在所述封装结构的位于所述凹部外部的第一侧上，其中面向所述封装结构的所述至少一个电连接器的表面可以设置在与所述第一电平不同的第二电平处。
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公开(公告)号：US09856136B2
公开(公告)日：2018-01-02
申请号：US13910133
申请日：2013-06-05
发明人： Thorsten Meyer , Gerald Ofner , Christian Mueller , Reinhard Mahnkopf , Christian Geissler , Andreas Augustin
CPC分类号： B81B7/0077 , B81B7/007 , B81B2207/012 , B81B2207/095 , B81C1/00333 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16146 , H01L2224/16227 , H01L2224/24137 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73259 , H01L2224/73267 , H01L2924/1431 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.
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公开(公告)号：US09646856B2
公开(公告)日：2017-05-09
申请号：US14715928
申请日：2015-05-19
IPC分类号： H01L21/02 , H01L21/304 , H01L21/56 , H01L23/31 , H01L23/00 , H01L21/311 , H01L21/683 , H01L21/78
CPC分类号： H01L21/561 , H01L21/02013 , H01L21/02016 , H01L21/304 , H01L21/311 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3107 , H01L23/3121 , H01L23/3135 , H01L23/3157 , H01L23/3185 , H01L24/02 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2221/68327 , H01L2223/6677 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/73267 , H01L2924/01029 , H01L2924/12042 , H01L2924/1461 , H01L2924/18162 , H01L2924/2064 , H01L2924/00
摘要： A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.
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4.发明申请SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING SETS 有权半导体器件及制造包含研磨组的半导体器件的方法公开(公告)号：US20150262844A1
公开(公告)日：2015-09-17
申请号：US14715928
申请日：2015-05-19
IPC分类号： H01L21/56 , H01L23/00 , H01L23/31 , H01L21/304 , H01L21/311 , H01L21/78 , H01L21/683
CPC分类号： H01L21/561 , H01L21/02013 , H01L21/02016 , H01L21/304 , H01L21/311 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3107 , H01L23/3121 , H01L23/3135 , H01L23/3157 , H01L23/3185 , H01L24/02 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2221/68327 , H01L2223/6677 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/73267 , H01L2924/01029 , H01L2924/12042 , H01L2924/1461 , H01L2924/18162 , H01L2924/2064 , H01L2924/00
摘要： A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.
摘要翻译： 一种制造器件的方法包括提供具有第一面和与第一面相对的第二面的半导体芯片，其具有布置在第一面上的接触焊盘。 将半导体芯片放置在载体上，其第一面朝向载体。 半导体芯片用封装材料封装。 移除载体，并且半导体材料从第一半导体芯片的第二面去除，而不会同时去除封装材料。
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公开(公告)号：US08907480B2
公开(公告)日：2014-12-09
申请号：US13802848
申请日：2013-03-14
发明人： Thorsten Meyer , Hans-Joachim Barth , Reinhard Mahnkopf , Sven Albers , Andreas Augustin , Christian Mueller
CPC分类号： H01L24/17 , H01L23/5256 , H01L23/5382 , H01L25/0657 , H01L2224/02379 , H01L2224/0401 , H01L2224/0557 , H01L2224/131 , H01L2224/16146 , H01L2224/1703 , H01L2224/17107 , H01L2224/17154 , H01L2224/17181 , H01L2224/17517 , H01L2224/81193 , H01L2924/12042 , H01L2924/014 , H01L2924/00
摘要： A chip arrangement may include: a first chip including a first contact, a second contact, and a redistribution structure electrically coupling the first contact to the second contact; a second chip including a contact; and a plurality of interconnects electrically coupled to the second contact of the first chip, wherein at least one interconnect of the plurality of interconnects electrically couples the second contact of the first chip to the contact of the second chip.
摘要翻译： 芯片布置可以包括：第一芯片，其包括第一触点，第二触点和将第一触点电耦合到第二触点的再分配结构; 包括触点的第二芯片; 以及电耦合到第一芯片的第二触点的多个互连，其中多个互连件中的至少一个互连将第一芯片的第二触点电耦合到第二芯片的触点。
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公开(公告)号：US20140106507A1
公开(公告)日：2014-04-17
申请号：US13828541
申请日：2013-03-14
发明人： Thorsten Meyer
IPC分类号： H01L23/00
CPC分类号： H01L22/10 , G03F7/70991 , G03F9/7003 , G03F9/7011 , H01L21/568 , H01L24/19 , H01L24/64 , H01L24/96 , H01L2224/02311 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/11013 , H01L2224/12105 , H01L2224/13006 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2924/12042 , H01L2924/014 , H01L2924/00
摘要： A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.
摘要翻译： 处理半导体芯片的方法包括：利用扫描仪测量放置在载体上的半导体管芯的位置，以产生管芯位置信息。 该方法包括在半导体管芯上方施加电介质层并将管芯位置信息传送到激光器组件。 该方法包括：基于由扫描器产生的管芯位置信息，将激光器组件与载体对准，激光器与激光器组件结合介电层。
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7.发明授权Chip interposer, semiconductor device, and method for manufacturing a semiconductor device 有权芯片插入器，半导体器件和半导体器件的制造方法公开(公告)号：US09263376B2
公开(公告)日：2016-02-16
申请号：US13862524
申请日：2013-04-15
发明人： Thorsten Meyer , Gerald Ofner
IPC分类号： H01L23/48 , H01L23/498 , H01L23/00
CPC分类号： H01L23/498 , H01L23/13 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/81 , H01L2224/0345 , H01L2224/0401 , H01L2224/05166 , H01L2224/05171 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/10175 , H01L2224/1132 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11474 , H01L2224/11849 , H01L2224/11903 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13561 , H01L2224/136 , H01L2224/1403 , H01L2224/141 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/171 , H01L2224/17104 , H01L2224/81193 , H01L2224/81203 , H01L2224/81385 , H01L2224/814 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81466 , H01L2224/81471 , H01L2224/81484 , H01L2224/81801 , H01L2924/12042 , H01L2924/1461 , H01L2924/381 , H01L2924/3841 , H01L2924/00 , H01L2924/014 , H01L2924/00015 , H01L2924/00014 , H01L2924/01074 , H01L2924/00012 , H01L2924/01013
摘要： A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad.
摘要翻译： 芯片插入器可以包括：第一互连级，包括第一焊盘; 以及包括第二焊盘的第二互连级别，其中所述第二焊盘可以面向与所述第一焊盘相同的方向。
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公开(公告)号：US20150061130A1
公开(公告)日：2015-03-05
申请号：US14535373
申请日：2014-11-07
发明人： Thorsten Meyer
IPC分类号： H01L25/065 , H01L21/56 , H01L25/00 , H01L23/538
CPC分类号： H01L25/0657 , H01L21/4846 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/525 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/73209 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00 , H01L2224/81
摘要： A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer; and a third semiconductor chip disposed at at least one of the second side of the second semiconductor chip and the second side of the encapsulation layer, the third semiconductor chip having a first side and a second side opposite the first side, the second side of the third semiconductor chip facing in the same direction as the second side of the second semiconductor chip and the second side of the encapsulation layer.
摘要翻译： 芯片布置可以包括：具有第一侧和与第一侧相对的第二侧的第一半导体芯片; 第二半导体芯片，具有与第一侧相对的第一侧和第二侧，第二半导体芯片设置在第一半导体芯片的第一侧并电耦合到第一半导体芯片，第二半导体芯片的第一侧面向第一半导体芯片 第一半导体芯片的第一面; 至少部分地封装所述第一半导体芯片和所述第二半导体芯片的封装层，所述封装层具有与所述第一侧相对的第一侧和第二侧，所述第二侧面向与所述第二半导体芯片的所述第二侧相同的方向 ; 互连结构，其至少部分地设置在所述封装层内并电耦合到所述第一和第二半导体芯片中的至少一个，其中所述互连结构可以延伸到所述封装层的第二侧; 以及第三半导体芯片，其设置在所述第二半导体芯片的所述第二侧和所述封装层的所述第二侧中的至少一个上，所述第三半导体芯片具有第一侧和与所述第一侧相对的第二侧， 第三半导体芯片面向与第二半导体芯片的第二侧相同的方向和封装层的第二面。
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公开(公告)号：US09312198B2
公开(公告)日：2016-04-12
申请号：US13833514
申请日：2013-03-15
发明人： Thorsten Meyer , Sven Albers , Andreas Wolter
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/31 , H01L25/065 , H01L25/03 , H01L25/00 , H01L21/66 , H01L25/10
CPC分类号： H01L25/105 , H01L21/568 , H01L22/14 , H01L23/31 , H01L23/3107 , H01L23/3135 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/03 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/18 , H01L2224/19 , H01L2224/24226 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/81005 , H01L2224/83005 , H01L2224/83192 , H01L2224/92244 , H01L2225/06517 , H01L2225/06524 , H01L2225/06548 , H01L2225/06572 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/1533 , H01L2924/181 , H01L2924/18161 , H01L2924/19107 , H01L2924/00 , H01L2224/16225 , H01L2924/00012
摘要： An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.
摘要翻译： 电子封装包括插入器，附接到插入件的第一侧的管芯，附接到插入件的第二侧的嵌入式电子封装，封装化合物，从电子封装的第一侧提供电路径的一组通孔 通过所述封装化合物施加到所述插入件，以及再分布层，电再重分配所述一组通孔以形成一组互连焊盘。 芯片或嵌入式电子封装或两者都电连接到插入器。
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公开(公告)号：US20160048086A1
公开(公告)日：2016-02-18
申请号：US14887111
申请日：2015-10-19
发明人： Thorsten Meyer
IPC分类号： G03F7/20
CPC分类号： G03F7/70433 , G03F7/70991 , G03F9/7003 , G03F9/7011 , H01L21/268 , H01L21/324 , H01L21/568 , H01L24/19 , H01L24/95 , H01L24/96 , H01L2224/05001 , H01L2224/05026 , H01L2224/05027 , H01L2224/05548 , H01L2224/12105 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.
摘要翻译： 处理半导体芯片的方法包括：利用扫描仪测量放置在载体上的半导体管芯的位置，以产生管芯位置信息。 该方法包括在半导体管芯上方施加电介质层并将管芯位置信息传送到激光器组件。 该方法包括：基于由扫描仪产生的管芯位置信息，将激光器组件与载体对准，激光器与激光器组件结合介电层。
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