公开(公告)号：US20140090596A1

公开(公告)日：2014-04-03

申请号：US14096981

申请日：2013-12-04

Applicant: Intermolecular, Inc.

Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: G01R31/28

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20130065796A1

公开(公告)日：2013-03-14

申请号：US13664119

申请日：2012-10-30

Applicant: INTERMOLECULAR, INC.

Inventor： Aaron T. Francis ,  Tony P. Chiang ,  John Schmidt ,  Kurt H. Weiner

IPC: C40B60/00

CPC classification number: C23C16/45514 ,  C23C16/45574 ,  C23C16/52 ,  H01L21/67017 ,  H01L21/67276 ,  Y10S438/907 ,  Y10S438/908 ,  Y10S438/913 ,  Y10T137/4673 ,  Y10T137/469 ,  Y10T137/87249 ,  Y10T137/87265 ,  Y10T137/87281

Abstract: An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.

Abstract translation: 描述了一种集成处理工具，其包括全晶片处理模块和组合处理模块。 用于组合处理模块的化学品从包括一组第一歧管的递送系统进料。 每个第一歧管的输出端连接至至少一个混合容器。 每个混合容器的输出馈送一组第二歧管中的多于一个。 每组第二歧管的输出馈送组合处理模块的多个位置隔离反应器中的一个。

公开(公告)号：US20140315332A1

公开(公告)日：2014-10-23

申请号：US14321663

申请日：2014-07-01

Applicant: Intermolecular, Inc.

Inventor： Gustavo A. Pinto ,  Tony P. Chiang ,  Kurt H. Weiner

IPC: H01L21/66

CPC classification number: H01L22/10 ,  H01L21/67005 ,  H01L22/34

Abstract: The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.

Abstract translation: 本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。 测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。 用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。 在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。 测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

公开(公告)号：US08603245B2

公开(公告)日：2013-12-10

申请号：US13657006

申请日：2012-10-22

Applicant: Intermolecular, Inc.

Inventor： Aaron T. Francis ,  Kurt H. Weiner

IPC: C23C16/00 ,  H01L21/306

CPC classification number: H01L21/67126

Abstract: Substrate processing systems and methods are described for site-isolated processing of substrates. The processing systems include numerous site-isolated reactors (SIRs). The processing systems include a reactor block having a cell array that includes numerous SIRs. A sleeve is coupled to an interior of each of the SIRs. The sleeve includes a compliance device configured to dynamically control a vertical position of the sleeve in the SIR. A sealing system is configured to provide a seal between a region of a substrate and the interior of each of the SIRs. The processing system can include numerous modules that comprise one or more site-isolated reactors (SIRs) configured for one or more of molecular self-assembly and combinatorial processing of substrates.

Abstract translation: 基板处理系统和方法被描述用于基板的场隔离处理。 处理系统包括许多场地隔离反应器（SIR）。 处理系统包括具有包括大量SIR的单元阵列的反应器块。 套筒连接到每个SIR的内部。 套筒包括配置成在SIR中动态地控制套筒的垂直位置的顺应装置。 密封系统被配置为在衬底的区域和每个SIR的内部之间提供密封。 处理系统可以包括多个模块，其包括被配置用于衬底的分子自组装和组合处理中的一个或多个的一个或多个位置隔离反应器（SIR）。

公开(公告)号：US08501505B2

公开(公告)日：2013-08-06

申请号：US13731715

申请日：2012-12-31

Applicant: Intermolecular, Inc.

Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

公开(公告)号：US20130285695A1

公开(公告)日：2013-10-31

申请号：US13932640

申请日：2013-07-01

Applicant: Intermolecular, Inc.

Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: G01R31/28

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

公开(公告)号：US20130138380A1

公开(公告)日：2013-05-30

申请号：US13731715

申请日：2012-12-31

Applicant: INTERMOLECULAR, INC.

Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: G01R31/28

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20130042810A1

公开(公告)日：2013-02-21

申请号：US13656118

申请日：2012-10-19

Applicant: INTERMOLECULAR, INC.

Inventor： Rick Endo ,  James Tsung ,  Kurt H. Weiner

IPC: C23C16/04

CPC classification number: H01L21/67225 ,  C23C16/042 ,  H01L21/6719 ,  H01L21/68742 ,  Y10S206/832

Abstract: A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extensions for the mask enable independent movement of the wafer and the mask. In one embodiment, the extensions are affixed to an annular ring which is capable of moving in a vertical direction within the processing chamber. A processing chamber, a mask, and a method for combinatorially processing a substrate are also provided.

Abstract translation: 提供了用于在处理室中独立地支撑晶片和掩模的结构。 该结构包括一组用于支撑晶片的延伸部和一组支撑该掩模的延伸部。 用于晶片的一组扩展和用于掩模的一组扩展使得能够独立地移动晶片和掩模。 在一个实施例中，延伸部固定到能够在处理室内沿垂直方向移动的环形环。 还提供了处理室，掩模和用于组合处理衬底的方法。

公开(公告)号：US20130039813A1

公开(公告)日：2013-02-14

申请号：US13657006

申请日：2012-10-22

Applicant: Intermolecular, Inc.

Inventor： Aaron T. Francis ,  Kurt H. Weiner

IPC: B01J19/24

CPC classification number: H01L21/67126

Abstract: Substrate processing systems and methods are described for site-isolated processing of substrates. The processing systems include numerous site-isolated reactors (SIRs). The processing systems include a reactor block having a cell array that includes numerous SIRs. A sleeve is coupled to an interior of each of the SIRs. The sleeve includes a compliance device configured to dynamically control a vertical position of the sleeve in the SIR. A sealing system is configured to provide a seal between a region of a substrate and the interior of each of the SIRs. The processing system can include numerous modules that comprise one or more site-isolated reactors (SIRs) configured for one or more of molecular self-assembly and combinatorial processing of substrates.

Abstract translation: 基板处理系统和方法被描述用于基板的场隔离处理。 处理系统包括许多场地隔离反应器（SIR）。 处理系统包括具有包括大量SIR的单元阵列的反应器块。 套筒连接到每个SIR的内部。 套筒包括配置成在SIR中动态地控制套筒的垂直位置的顺应装置。 密封系统被配置为在衬底的区域和每个SIR的内部之间提供密封。 处理系统可以包括多个模块，其包括被配置用于衬底的分子自组装和组合处理中的一个或多个的一个或多个位置隔离反应器（SIR）。

公开(公告)号：US08633039B2

公开(公告)日：2014-01-21

申请号：US13932640

申请日：2013-07-01

Applicant: Intermolecular, Inc.

Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。