公开(公告)号：US10224419B2

公开(公告)日：2019-03-05

申请号：US15823022

申请日：2017-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L27/11529

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US09922984B1

公开(公告)日：2018-03-20

申请号：US15616131

申请日：2017-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L21/8258 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US09287000B1

公开(公告)日：2016-03-15

申请号：US14748473

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Derrick Liu ,  Chun-Chen Yeh

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C11/40

CPC classification number: G11C17/18 ,  G11C11/40 ,  G11C17/16 ,  H01L27/11206

Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.

Abstract translation: 提供了一种用于对在源极和漏极之间具有源极，漏极，栅极和沟道区域的晶体管进行编程的技术。 栅极位于沟道区上方的介质上方。 栅极电压大约等于或大于栅极电介质的击穿电压，以便将栅极电介质分解成击穿状态。 源极和漏极之间的电流由于分解栅极电介质而流动。 响应晶体管被编程，在源极和漏极之间流动的电流不是基于栅极处的栅极电压。

公开(公告)号：US10121852B2

公开(公告)日：2018-11-06

申请号：US15794616

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US09876074B2

公开(公告)日：2018-01-23

申请号：US14719829

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20150357512A1

公开(公告)日：2015-12-10

申请号：US14828663

申请日：2015-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L51/00 ,  H01L33/42 ,  H01L31/0224 ,  H01L33/00

CPC classification number: H01L31/1884 ,  B82Y10/00 ,  B82Y30/00 ,  H01B1/24 ,  H01L31/022408 ,  H01L31/022425 ,  H01L31/022466 ,  H01L33/005 ,  H01L33/42 ,  H01L51/0021 ,  H05K3/105 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2203/1194 ,  Y02E10/50

Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.

Abstract translation: 公开了具有金属硅化物透明导电电极的结构的实施例，其具有商业上可行性，稳健且安全使用，并且因此最佳地结合到诸如平板显示器，触摸面板，太阳能电池，发光二极管 LED），有机光电子器件等。具体地，该结构可以包括衬底（例如，玻璃或塑料衬底）和该衬底上的透明导电膜。 透明导电膜可以包括金属硅化物纳米线网络。 例如，在一个实施例中，金属硅化物纳米线网络可以包括以无序布置融合在一起的多个金属硅化物纳米线，使得它们形成网状物。 在另一个实施例中，金属硅化物纳米线网络可以包括图案化的多个金属硅化物纳米线，使得它们形成网格。 本文还公开了用于形成这种结构的各种不同的方法实施例。

公开(公告)号：US11282186B2

公开(公告)日：2022-03-22

申请号：US16822471

申请日：2020-03-18

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Liying Jiang ,  Derrick Liu ,  Jingyun Zhang ,  Huimei Zhou

IPC: G06T7/00 ,  G06N20/00 ,  G06K9/62 ,  G06V10/44 ,  G06K9/00 ,  G06F16/28

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

公开(公告)号：US11056610B2

公开(公告)日：2021-07-06

申请号：US16053959

申请日：2018-08-03

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L31/0224 ,  H01L33/00 ,  H01L33/42 ,  H01L51/00 ,  B82Y10/00 ,  H01B1/24 ,  H05K3/10 ,  B82Y30/00

Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

公开(公告)号：US10263098B2

公开(公告)日：2019-04-16

申请号：US15787768

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L27/11529

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US10170477B2

公开(公告)日：2019-01-01

申请号：US14934758

申请日：2015-11-06

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Gauri Karve ,  Derrick Liu ,  Robert R. Robison ,  Gen Tsutsui ,  Reinaldo A. Vega ,  Koji Watanabe

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/40

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.