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    INTEGRATED CIRCUIT VOLTAGE-CONTROLLED OSCILLATOR WITH LATE-STAGE FABRICATION TUNING
    1.
    发明申请
    INTEGRATED CIRCUIT VOLTAGE-CONTROLLED OSCILLATOR WITH LATE-STAGE FABRICATION TUNING 审中-公开

    公开(公告)号：US20190386614A1

    公开(公告)日：2019-12-19

    申请号：US16011793

    申请日：2018-06-19

    Applicant: International Business Machines Corporation

    Inventor： Grant P. Kesselring ,  James Strom ,  Scott Trcka ,  Ann Chen Wu

    IPC: H03B5/12 ,  H03L7/099

    Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

    Differential Phase-Frequency Detector
    2.
    发明申请
    Differential Phase-Frequency Detector 审中-公开

    公开(公告)号：US20180109265A1

    公开(公告)日：2018-04-19

    申请号：US15843575

    申请日：2017-12-15

    Applicant: International Business Machines Corporation

    Inventor： David M. Friend ,  Grant P. Kesselring ,  James D. Strom ,  Alan P. Wagstaff

    IPC: H03L7/085 ,  H03L7/089

    CPC classification number: H03L7/085 ,  H03L7/089

    Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.

    VARIABLE FREQUENCY OSCILLATOR WITH SPECIALIZED INVERTER STAGES
    3.
    发明申请
    VARIABLE FREQUENCY OSCILLATOR WITH SPECIALIZED INVERTER STAGES 有权
    具有专用逆变器级的可变频率振荡器

    公开(公告)号：US20150171790A1

    公开(公告)日：2015-06-18

    申请号：US14109364

    申请日：2013-12-17

    Applicant: International Business Machines Corporation

    Inventor： Andrew D. Davies ,  Joel T. Ficke ,  David M. Friend ,  Grant P. Kesselring ,  James D. Strom

    IPC: H03B5/12

    CPC classification number: H03B5/124 ,  H03K3/0315 ,  H03K3/354

    Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

    Abstract translation: 可变频率振荡器装置包括：第一反相器级，其被设计成通过使用电流源对电容器进行充电和放电来反转输入信号以产生锯齿波信号，所述电流源各自提供响应于控制信号的相应量的电流， 衰减信号。 第二反相器级被设计为从第一反相器级的锯齿波信号产生第一反相信号。 第三反相器级被设计为从第一反相信号产生第二反相信号，并且基于控制信号抑制第一反相信号的信号转变速率。

    Guard ring monitor
    4.
    发明授权
    Guard ring monitor 有权

    公开(公告)号：US10969422B2

    公开(公告)日：2021-04-06

    申请号：US15981175

    申请日：2018-05-16

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Grant P. Kesselring ,  James D. Strom ,  Ann Chen Wu

    IPC: G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  G01R31/00 ,  H01L23/522 ,  H01L23/528

    Abstract: An embodiment of the invention may include a method and structure for determining a failure in a guard ring of a chip. The method may include measuring a current frequency of oscillation of a crack check circuit located within a guard ring. The method may include comparing the frequency to a baseline frequency of oscillation of the crack check circuit. The current frequency and baseline frequency may be normalized using a set of bypass lines. The method may include determining there is a failure of the guard ring based on the difference between the normalized frequency of oscillation and the baseline normalized frequency of oscillation.

    Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)
    6.
    发明授权
    Implementing dynamic phase error correction method and circuit for phase locked loop (PLL) 有权
    实现锁相环（PLL）的动态相位误差校正方法和电路

    公开(公告)号：US09264052B1

    公开(公告)日：2016-02-16

    申请号：US14600396

    申请日：2015-01-20

    Applicant: International Business Machines Corporation

    Inventor： Grant P. Kesselring ,  Christopher W. Steffen ,  James D. Strom

    IPC: H03L7/06 ,  H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/081

    Abstract: A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.

    Abstract translation: 一种用于实现锁相环（PLL）电路的动态相位误差校正的方法和电路，以及设置有被摄体电路的设计结构。 该电路实现动态相位误差校正，并包括一个可调延迟线，放置在参考或反馈时钟路径中。 相位误差校正电路检测PLL中参考时钟路径从输入引脚到相位检波器的传播延迟。 它还检测PLL中的输入引脚到相位频率检测器的反馈时钟路径的传播延迟。 比较检测到的传播延迟，并产生与失配成比例的控制信号。 控制信号被施加到可调延迟线。 延迟线的延迟被连续调节，直到参考和反馈时钟路径平衡。

    DEVICE MISMATCH MITIGATION FOR MEDIUM RANGE AND BEYOND DISTANCES
    8.
    发明申请
    DEVICE MISMATCH MITIGATION FOR MEDIUM RANGE AND BEYOND DISTANCES 有权

    公开(公告)号：US20220406769A1

    公开(公告)日：2022-12-22

    申请号：US17354469

    申请日：2021-06-22

    Applicant: International Business Machines Corporation

    Inventor： Dureseti Chidambarrao ,  Matthew Stephen Angyal ,  Noah Zamdmer ,  Varadarajan Vidya ,  James Strom ,  Grant P. Kesselring ,  Erik Unterborn

    IPC: H01L27/02

    Abstract: A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

    Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning
    10.
    发明授权
    Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning 有权

    公开(公告)号：US10778146B2

    公开(公告)日：2020-09-15

    申请号：US16011793

    申请日：2018-06-19

    Applicant: International Business Machines Corporation

    Inventor： Grant P. Kesselring ,  James Strom ,  Scott Trcka ,  Ann Chen Wu

    IPC: H03B5/12 ,  H03L7/099 ,  H05K1/02

    Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

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