公开(公告)号：US10957850B2

公开(公告)日：2021-03-23

申请号：US16151401

申请日：2018-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Isabel Cristina Chu ,  Son Nguyen ,  Michael Rizzolo ,  John C. Arnold

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.

公开(公告)号：US20200119089A1

公开(公告)日：2020-04-16

申请号：US16159220

申请日：2018-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Theodorus E. Standaert ,  Isabel Cristina Chu ,  Chih-Chao Yang ,  Son Nguyen

IPC: H01L27/22

Abstract: A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.

公开(公告)号：US10672618B2

公开(公告)日：2020-06-02

申请号：US16032759

申请日：2018-07-11

Applicant: Tokyo Electron Limited ,  International Business Machines Corporation

Inventor： Vinh Luong ,  Isabel Cristina Chu ,  Ashim Dutta

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01J37/32

Abstract: Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

公开(公告)号：US10312140B1

公开(公告)日：2019-06-04

申请号：US15847005

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Isabel Cristina Chu ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Ekmini Anuja De Silva ,  Gauri Karve ,  Fee Li Lie ,  Nicole Adelle Saulnier ,  Indira Seshadri ,  Hosadurga Shobha

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/76819 ,  H01L21/76877 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53228

Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.

公开(公告)号：US10832945B2

公开(公告)日：2020-11-10

申请号：US16277528

申请日：2019-02-15

Applicant: International Business Machines Corporation

Inventor： Nicole Saulnier ,  Indira Seshadri ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Gauri Karve ,  Fee Li Lie ,  Isabel Cristina Chu ,  Hosadurga Shobha ,  Ekmini A. De Silva

IPC: H01L21/768 ,  H01L21/311

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

公开(公告)号：US20190189503A1

公开(公告)日：2019-06-20

申请号：US15847005

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Isabel Cristina Chu ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Ekmini Anuja De Silva ,  Gauri Karve ,  Fee Li Lie ,  Nicole Adelle Saulnier ,  Indira Seshadri ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76837 ,  H01L21/76819 ,  H01L21/76877 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53228

Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.

公开(公告)号：US20200266100A1

公开(公告)日：2020-08-20

申请号：US16277528

申请日：2019-02-15

Applicant: International Business Machines Corporation

Inventor： Nicole Saulnier ,  Indira Seshadri ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Gauri Karve ,  Fee Li Lie ,  Isabel Cristina Chu ,  Hosadurga Shobha ,  Ekmini A. De Silva

IPC: H01L21/768 ,  H01L21/311

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

公开(公告)号：US10692925B2

公开(公告)日：2020-06-23

申请号：US16159220

申请日：2018-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Theodorus E. Standaert ,  Isabel Cristina Chu ,  Chih-Chao Yang ,  Son Nguyen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.

公开(公告)号：US20190189504A1

公开(公告)日：2019-06-20

申请号：US16286072

申请日：2019-02-26

Applicant: International Business Machines Corporation

Inventor： Isabel Cristina Chu ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Ekmini Anuja De Silva ,  Gauri Karve ,  Fee Li Lie ,  Nicole Adelle Saulnier ,  Indira Seshadri ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/66 ,  H01L23/522

CPC classification number: H01L21/76837 ,  H01L21/76819 ,  H01L21/76877 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53228

Abstract: Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.