摘要:
A semiconductor structure comprises a substrate, a patch of optically tunable material disposed over the substrate, a first electrode coupled to the patch of optically tunable material and a switch providing a current source, and a second electrode coupled to the patch of optically tunable material and a ground voltage. The first electrode and the second electrode are configured to modify a state of the patch of optically tunable material to adjust a reflectivity of the patch of optically tunable material.
摘要:
A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.
摘要:
An apparatus includes two or more electrically rotatable antennas providing a reconfigurable metasurface, each of the electrically rotatable antennas including a disk of optically tunable material. The apparatus also includes a control circuit including a plurality of switches each coupled to (i) one of a plurality of electrodes, the plurality of electrodes being arranged proximate different portions of at least one surface of each of the disks of optically tunable material and (ii) to at least one of a current source and a ground voltage. The control circuit is configured to modify states of portions of the optically tunable material in each of the disks of optically tunable material utilizing current supplied between at least two of the plurality of electrodes to adjust reflectivity of the portions of the optically tunable material to dynamically reconfigure respective antenna shape configurations of each of the electrically rotatable antennas.
摘要:
A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.
摘要:
A method to generate chemo-epitaxy masks includes receiving a device pattern comprising a plurality of device geometries, wherein the device pattern conforms to chemo-epitaxy constraints, enlarging the device geometries along a width of the device geometries to provide enlarged device geometries, and using the enlarged device geometries to generate at least one chemo-epitaxy mask corresponding to the device pattern. The at least one chemo-epitaxy mask may include a neutral hard mask and one or more cut masks. The method may also include bridging device geometries that are within a selected distance along a length of the device geometries and merging device geometries that overlap. The method may also include filling break regions between the device geometries with a neutral fill pattern. A corresponding computer program product and computer system are also disclosed herein.
摘要:
A method to generate chemo-epitaxy masks includes receiving a device pattern comprising a plurality of device geometries, wherein the device pattern conforms to chemo-epitaxy constraints, enlarging the device geometries along a width of the device geometries to provide enlarged device geometries, and using the enlarged device geometries to generate at least one chemo-epitaxy mask corresponding to the device pattern. The at least one chemo-epitaxy mask may include a neutral hard mask and one or more cut masks. The method may also include bridging device geometries that are within a selected distance along a length of the device geometries and merging device geometries that overlap. The method may also include filling break regions between the device geometries with a neutral fill pattern. A corresponding computer program product and computer system are also disclosed herein.
摘要:
A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.
摘要:
A design layout including shapes of target areas for forming semiconductor fins employing directed self-assembly can be decomposed into guiding patterns and cut patterns. The lengthwise edges of the shapes of target areas are adjusted. Widthwise edges of the adjusted shapes are extended outward to generate diffusion shapes. Guiding pattern shapes are then generated employing the diffusion shapes. Taper edges are adjusted based on process bias of a photoresist material to be subsequently employed. Optionally, a portion of a guiding pattern shape between diffusion shapes may be removed as a connection shape. The guiding pattern shapes can define at least one guiding pattern mask for lithographic pattern of guiding pattern shapes, and cut shapes can be derived from the diffusion shapes and the guiding pattern shapes. The guiding pattern shapes and the cut shapes may be adjusted to accommodate effects at device cell edges and at device macro edges.
摘要:
Methods and systems for generating a random number include extracting feature information from a structure having a random physical configuration. The feature information is converted to a string of binary values to generate a random number. Pseudo-random numbers are generated using the random number as a seed to improve the security of encrypted information.
摘要:
A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising: inserting a first external dummy along an external edge of the guiding pattern in a vertical direction; and inserting a second external dummy at a fixed distance from a second edge of the first external dummy, wherein the second external dummy includes a two-dimensional shape such that at least two edges of the second external dummy are parallel to the second edge of the first external dummy.