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    PHYSICALLY DETECTABLE ID INTRODUCED BY LITHOGRAPHY SRAF INSERTION FOR HETEROGENEOUS INTEGRATION
    2.
    发明公开
    PHYSICALLY DETECTABLE ID INTRODUCED BY LITHOGRAPHY SRAF INSERTION FOR HETEROGENEOUS INTEGRATION 审中-公开

    公开(公告)号：US20240201583A1

    公开(公告)日：2024-06-20

    申请号：US18083851

    申请日：2022-12-19

    Applicant: International Business Machines Corporation

    Inventor： Cheng Chi ,  Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  David Wolpert

    IPC: G03F7/00 ,  G03F7/09 ,  G03F7/20 ,  G06K19/06

    CPC classification number: G03F7/0005 ,  G03F7/09 ,  G03F7/2047 ,  G03F7/70325 ,  G06K19/06028 ,  G06K19/06037

    Abstract: A system and method of leveraging sub-resolution assist feature (SRAF) to intentionally distort a feature of a pattern for identification and security purposes. A method of forming an identifier on a semiconductor structure includes: receiving, at a semiconductor manufacturing foundry, a specification of an identifier including a pattern comprising a combination of main features; designing a lithographic mask structure based on the received identifier specification, the lithographic mask structure including mask features corresponding to the specified main features and at least one sub-resolution assist feature (SRAF) structure in a geometrical relationship with a corresponding mask feature for forming, using a lithography process, a uniquely modified identifier pattern comprising a combination of modified main features; and then subsequently lithographically exposing, employing the mask structure, photoresist layers at an optical condition and subsequently developing the photoresist layers to transfer the uniquely modified identifier pattern to a surface of a semiconductor wafer.

    DIELECTRIC TUNING OF NEGATIVE CAPACITANCE IN DUAL CHANNEL FIELD EFFECT TRANSISTORS
    3.
    发明公开
    DIELECTRIC TUNING OF NEGATIVE CAPACITANCE IN DUAL CHANNEL FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20230282523A1

    公开(公告)日：2023-09-07

    申请号：US17688873

    申请日：2022-03-07

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  REINALDO VEGA ,  Praneet Adusumilli ,  Cheng Chi

    IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/49

    CPC classification number: H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/4958 ,  H01L29/4966

    Abstract: A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

    MULTILAYER DIELECTRIC FOR METAL-INSULATOR-METAL CAPACITOR
    5.
    发明申请
    MULTILAYER DIELECTRIC FOR METAL-INSULATOR-METAL CAPACITOR 有权

    公开(公告)号：US20220392995A1

    公开(公告)日：2022-12-08

    申请号：US17341489

    申请日：2021-06-08

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  REINALDO VEGA ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

    IPC: H01L49/02 ,  H01L29/51

    Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

    Resistance drift mitigation in non-volatile memory cell
    6.
    发明授权
    Resistance drift mitigation in non-volatile memory cell 有权

    公开(公告)号：US11430954B2

    公开(公告)日：2022-08-30

    申请号：US17106286

    申请日：2020-11-30

    Applicant: International Business Machines Corporation

    Inventor： Praneet Adusumilli ,  Anirban Chandra ,  Takashi Ando ,  Cheng Chi ,  Reinaldo Vega

    IPC: H01L45/00

    Abstract: A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

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