公开(公告)号：US11673766B2

公开(公告)日：2023-06-13

申请号：US16173781

申请日：2018-10-29

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Tara Astigarraga ,  Eric Miller ,  Kangguo Cheng ,  Fee Li Lie ,  Sean Teehan ,  Marc Bergendahl

IPC: B66B1/46 ,  B66B1/24 ,  B66B5/00

CPC classification number: B66B1/2458 ,  B66B1/468 ,  B66B5/0012 ,  B66B2201/103 ,  B66B2201/20 ,  B66B2201/222 ,  B66B2201/402 ,  B66B2201/403 ,  B66B2201/405 ,  B66B2201/4615 ,  B66B2201/4653 ,  B66B2201/4676

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

公开(公告)号：US11257716B2

公开(公告)日：2022-02-22

申请号：US16689621

申请日：2019-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael P. Belyansky ,  Marc Bergendahl ,  Victor W. C. Chan ,  Jeffrey C. Shearer

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/027

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

公开(公告)号：US11263059B2

公开(公告)日：2022-03-01

申请号：US16125466

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Jonathan Fry ,  Christopher J. Penny ,  Marc Bergendahl ,  Christopher J. Waskiewicz ,  Jean Wynne ,  James Demarest

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  H04L9/06

Abstract: An example operation may include one or more of connecting, by a load leveler, to a blockchain network comprising a plurality of nodes and configured to store a common work item, computing, by the load leveler, loads across the plurality of the nodes that need to execute the common work item upon completion of current tasks, determining, by the load leveler, a network load impact based on execution of a common blockchain consensus checking process on the network nodes, executing, by the load leveler, a work assessment process based on the loads computed across the plurality of the nodes and on the determined network load impact of the blockchain network, and assigning, by the load leveler, new tasks to the nodes based on results of the execution of the work assessment process.

公开(公告)号：US10923401B2

公开(公告)日：2021-02-16

申请号：US16172205

申请日：2018-10-26

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Marc Bergendahl ,  Ekmini A. De Silva ,  Alex Joseph Varghese ,  Yann Mignot ,  Matthew T. Shoudy ,  Gangadhara Raja Muthinti ,  Dallas Lea

IPC: H01L21/8234 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/3213

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

公开(公告)号：US20200006137A1

公开(公告)日：2020-01-02

申请号：US16020412

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Marc Bergendahl ,  Victor W. C. Chan ,  JEFFREY C. SHEARER

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

公开(公告)号：US11005646B2

公开(公告)日：2021-05-11

申请号：US15987700

申请日：2018-05-23

Applicant: International Business Machines Corporation

Inventor： Jonathan Fry ,  Christopher J. Penny ,  James Demarest ,  Marc Bergendahl ,  Jean Wynne ,  Christopher J. Waskiewicz

IPC: H04L9/06 ,  G06Q30/08 ,  G06Q40/04

Abstract: A blockchain may be used as a stochastic timer. The posting of a blockchain solution for verification may be a trigger that determines an event schedule. Because the only entity that knows when the solution will be posted is the solving entity, the solving entity may be rewarded with the ability to potentially exploit this knowledge. However, because the solving of a blockchain is a competitive process, there is a risk that if the solving entity retains the solution for greater exploitation, then another entity will post the solution and therefore gain the benefit. A blockchain stochastic timer can thus provide the necessary incentive for entities to invest computational resources into blockchain solutions.

公开(公告)号：US20200090998A1

公开(公告)日：2020-03-19

申请号：US16689621

申请日：2019-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael P. Belyansky ,  Marc Bergendahl ,  Victor W. C. Chan ,  JEFFREY C. SHEARER

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8238

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

公开(公告)号：US11222820B2

公开(公告)日：2022-01-11

申请号：US16020412

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Marc Bergendahl ,  Victor W. C. Chan ,  Jeffrey C. Shearer

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/027

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

公开(公告)号：US10692776B2

公开(公告)日：2020-06-23

申请号：US16181977

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Marc Bergendahl ,  Kangguo Cheng ,  Yann Mignot

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.

公开(公告)号：US20200144131A1

公开(公告)日：2020-05-07

申请号：US16181977

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Marc Bergendahl ,  Kangguo Cheng ,  Yann Mignot

IPC: H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.