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    UNIFORM HORIZONTAL SPACER
    5.
    发明申请
    UNIFORM HORIZONTAL SPACER 审中-公开

    公开(公告)号：US20200044054A1

    公开(公告)日：2020-02-06

    申请号：US16049930

    申请日：2018-07-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael P. Belyansky ,  Oleg Gluschenkov

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

    Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

    Vertical transport FET (VFET) with dual top spacer
    6.
    发明授权
    Vertical transport FET (VFET) with dual top spacer 有权

    公开(公告)号：US10388766B2

    公开(公告)日：2019-08-20

    申请号：US15791095

    申请日：2017-10-23

    Applicant: International Business Machines Corporation

    Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

    Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

    METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING A COMPRESSIVE NITRIDE LAYER
    7.
    发明申请
    METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING A COMPRESSIVE NITRIDE LAYER 审中-公开
    制造具有压缩性氮化物层的集成电路的方法

    公开(公告)号：US20140183720A1

    公开(公告)日：2014-07-03

    申请号：US13731305

    申请日：2012-12-31

    Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Scott Beasor ,  Jay Strane ,  Man Fai Ng ,  Brett H. Engel ,  Chang Yong Xiao ,  Michael P. Belyansky ,  Tsung-Liang Chen ,  Kyung Bum Koo

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/48 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

    Abstract translation: 公开了具有压缩氮化物层的半导体集成电路的制造方法。 在一个示例中，制造集成电路的方法包括在半导体衬底上沉积铝层，在铝层上沉积拉伸氮化硅层或中性氮化硅层，以及在抗拉氮化硅上沉积压缩氮化硅层 层或中性氮化硅层。 压缩氮化硅层以至少约为拉伸氮化硅层或中性氮化硅层厚度的约两倍的厚度沉积。 此外，在铝层和拉伸氮化硅层或中性氮化硅层之间的界面处，或者在拉伸氮化硅层或中性氮化硅层与压缩氮化物层之间的界面处没有分层存在。

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