公开(公告)号：US11869937B2

公开(公告)日：2024-01-09

申请号：US17578891

申请日：2022-01-19

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0657 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

公开(公告)号：US11869936B2

公开(公告)日：2024-01-09

申请号：US17402507

申请日：2021-08-14

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0657 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

公开(公告)号：US20190341490A1

公开(公告)日：2019-11-07

申请号：US16516477

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10424663B2

公开(公告)日：2019-09-24

申请号：US15813523

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H03K17/687 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10396181B2

公开(公告)日：2019-08-27

申请号：US16047042

申请日：2018-07-27

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US20190006506A1

公开(公告)日：2019-01-03

申请号：US15639721

申请日：2017-06-30

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：US20180342614A1

公开(公告)日：2018-11-29

申请号：US15602884

申请日：2017-05-23

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H03K17/687 ,  H01L29/06

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10083962B2

公开(公告)日：2018-09-25

申请号：US15256284

申请日：2016-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Sean Teehan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

公开(公告)号：US20180219101A1

公开(公告)日：2018-08-02

申请号：US15938367

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H05K999/99

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

公开(公告)号：US20180158818A1

公开(公告)日：2018-06-07

申请号：US15786828

申请日：2017-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.