公开(公告)号：US20150255343A1

公开(公告)日：2015-09-10

申请号：US14721361

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20140203435A1

公开(公告)日：2014-07-24

申请号：US13744705

申请日：2013-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09455186B2

公开(公告)日：2016-09-27

申请号：US14721361

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US09859208B1

公开(公告)日：2018-01-02

申请号：US15268604

申请日：2016-09-18

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Naftali E. Lustig ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/528

Abstract: A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.

公开(公告)号：US09406560B2

公开(公告)日：2016-08-02

申请号：US14721323

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20150255398A1

公开(公告)日：2015-09-10

申请号：US14721410

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US09385038B2

公开(公告)日：2016-07-05

申请号：US14721410

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20150255342A1

公开(公告)日：2015-09-10

申请号：US14721323

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09076847B2

公开(公告)日：2015-07-07

申请号：US13744705

申请日：2013-01-18

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US08927442B1

公开(公告)日：2015-01-06

申请号：US13951321

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Yannick S. Loquet ,  Yann A. Mignot ,  Son V. Nguyen ,  Muthumanickam Sankarapandian ,  Hosadurga Shobha

IPC: H01L21/469 ,  H01L23/58

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.

Abstract translation: 提供了一种用于制造具有渐变过渡层的改进的SiCOH硬掩模的结构和方法，其具有用于形成线路（BEOL）金属化互连的次20nm后端的改进的轮廓。 在一个实施例中，改进的硬掩模可以由五层组成：氧化物粘附层，渐变过渡层，电介质层，反向渐变过渡层和氧化物层。 在另一个实施例中，改进的硬掩模可以由四层构成; 氧化物粘附层，渐变过渡层，电介质层和氧化物层。 在另一个实施例中，形成改进的硬掩模的方法可以包括利用硅前体，致孔剂和氧气的连续五级等离子体增强化学气相沉积（PECVD）工艺。 在另一个实施例中，形成改进的硬掩模的方法可以包括利用硅前体，致孔剂和氧的连续四步PECVD工艺。