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    Multiple-depth trench interconnect technology at advanced semiconductor nodes
    1.
    发明授权
    Multiple-depth trench interconnect technology at advanced semiconductor nodes 有权

    公开(公告)号：US10169525B2

    公开(公告)日：2019-01-01

    申请号：US15619004

    申请日：2017-06-09

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC: G06F17/00 ,  G06F17/50 ,  H01L21/768 ,  H01L21/67 ,  G03F7/20 ,  H01L21/311

    Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

    EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN
    3.
    发明申请
    EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN 有权
    早期覆盖预测和覆盖面设计

    公开(公告)号：US20160378904A1

    公开(公告)日：2016-12-29

    申请号：US14753344

    申请日：2015-06-29

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

    Abstract translation: 各种实施例包括计算机实现的方法，用于分析表示用于叠加效果的集成电路（IC）的布局中的至少一个特征的计算机程序产品和系统。 在一些情况下，方法包括计算机实现的方法，包括：通过在形成表示IC之后的数据文件上运行化学机械抛光（CMP）模型，沉积模型或蚀刻模型中的至少一个来对IC的形貌进行建模 的最上层; 使用IC的地形模型对IC中的至少一个特征进行建模以获得覆盖效果; 以及响应于检测到所述至少一个特征中的覆盖效应，修改在形成最上层之后表示IC的数据文件，所述覆盖效应出现在最上层下面的层中。

    Early overlay prediction and overlay-aware mask design
    5.
    发明授权
    Early overlay prediction and overlay-aware mask design 有权

    公开(公告)号：US09940429B2

    公开(公告)日：2018-04-10

    申请号：US14753344

    申请日：2015-06-29

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

    Stitch-derived via structures and methods of generating the same
    6.
    发明授权
    Stitch-derived via structures and methods of generating the same 有权
    针迹衍生经结构及其生成方法

    公开(公告)号：US09454631B2

    公开(公告)日：2016-09-27

    申请号：US14285719

    申请日：2014-05-23

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522 ,  H01L21/768

    CPC classification number: G06F17/5068 ,  G06F17/50 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

    Abstract translation: 通过级别的设计形状被映射到上层导线级别的线级设计形状设计的针脚区域。 对于不对应于通孔级设计形状的每个针脚区域，在底层导电线路层中提供通孔捕捉设计形状。 可以调整针迹区域和通孔捕捉设计形状的形状以符合设计规则约束。 此外，针迹可以可选地移动到相邻的线级设计形状中以解决设计规则冲突。 一旦所有通孔级设计形状被相应的针脚区域替换，修改后的设计布局可以消除通孔级设计形状，从而不需要提供通孔级光刻掩模。 体现修改后的设计布局的金属互连结构可以通过采用一组硬掩模层而不使用用于通孔级的光刻掩模来形成。

    MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCED SEMICONDUCTOR NODES
    8.
    发明申请
    MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCED SEMICONDUCTOR NODES 有权
    先进的半导体节点的多深度互联互连技术

    公开(公告)号：US20160042114A1

    公开(公告)日：2016-02-11

    申请号：US14883243

    申请日：2015-10-14

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  G03F7/20 ,  H01L21/308 ,  H01L21/67 ,  H01L21/768 ,  H01L21/027

    CPC classification number: G06F17/5081 ,  G03F7/2022 ,  G06F17/5077 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/76802 ,  H01L21/76816

    Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

    Abstract translation: 金属互连结构，系统和制造方法，其中设计布局包括形成不同沟槽深度的至少两个沟槽的结果。 该方法使用稍微改进的BEOL处理堆，以防止金属互连结构侵入下面的硬掩模电介质或金属硬掩模层。 因此，通过调整系统的参数并且允许由两个掩模曝光的区域具有更深的沟槽来获得两个沟槽深度。 这里，通过使用定义最低蚀刻深度的硬掩模来修改BEOL堆叠处理以实现两个沟槽深度。 该设计可以通过利用辅助沟槽深度来优化用于电迁移（或设置定时违反）的设计的软件来优化，检查电线周围的空间机会，推出电线以产生空间并将电线转换成深沟槽线。

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