公开(公告)号：US20150255343A1

公开(公告)日：2015-09-10

申请号：US14721361

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20140203435A1

公开(公告)日：2014-07-24

申请号：US13744705

申请日：2013-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09385038B2

公开(公告)日：2016-07-05

申请号：US14721410

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20150363536A1

公开(公告)日：2015-12-17

申请号：US14306715

申请日：2014-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dureseti Chidambarrao ,  James A. Culp ,  Paul C. Parries ,  Ian P. Stobert

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G03F7/70433 ,  G03F7/70633

Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Abstract translation: 用于在半导体光刻掩模设计工艺流程期间减少重叠误差的装置，方法和计算机程序产品。 该方法获得表示光掩模布局设计的密度特性的数据; 基于所获得的密度特征数据预测应力诱导位移; 并通过指定各个照片掩模设计形状的移位移动来预测补偿预测的位移来校正掩模布局设计数据。 为了获得表示密度特性的数据，该方法合并组合的数据以制作光掩模以获得完整的掩模版场数据集。 合并包括表示密度特征驱动应力效应的数据的合并。 然后计算合并的掩模版数据的密度特性数据。 为了预测应力引起的位移，该方法将所述密度特征数据输入到预测作为密度的函数的位移的编程模型中，并输出预测的移位数据。

公开(公告)号：US20150310155A1

公开(公告)日：2015-10-29

申请号：US14261632

申请日：2014-04-25

Applicant: International Business Machines Corporation

Inventor： Shayak Banerjee ,  James A. Culp ,  Ian P. Stobert

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5068 ,  G06F2217/12

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Abstract translation: 各种实施例包括用于验证集成电路（IC）布局的计算机实现的方法，计算机程序产品和系统。 在某些情况下，方法包括验证IC布局的计算机实现的方法，该方法包括：获得关于IC布局中的至少一个物理特征的过程变化频带的数据; 确定所述IC布局中的所述至少一个物理特征的基于电压的过程变化带阈值; 基于IC布局中的至少一个物理特征的基于电压的过程变化带阈值来确定IC布局中的至少一个物理特征的过程变化带是否符合IC布局的设计规范; 以及响应于所述至少一个物理特征的所述过程变化带不符合所述设计规范的确定来修改所述IC布局。

公开(公告)号：US20150255342A1

公开(公告)日：2015-09-10

申请号：US14721323

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09076847B2

公开(公告)日：2015-07-07

申请号：US13744705

申请日：2013-01-18

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09406560B2

公开(公告)日：2016-08-02

申请号：US14721323

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US20150255398A1

公开(公告)日：2015-09-10

申请号：US14721410

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

公开(公告)号：US09455186B2

公开(公告)日：2016-09-27

申请号：US14721361

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.