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公开(公告)号：US20240362168A1
公开(公告)日：2024-10-31
申请号：US18307838
申请日：2023-04-27
发明人： Radu Ioan Stoica , Timothy J. Fisher , Nikolaos Papandreou , Roman Alexander Pletka , Aaron Daniel Fry , Charalampos Pozidis , Andrew D. Walls
IPC分类号： G06F12/1009
CPC分类号： G06F12/1009
摘要： A computer-implemented method, a computer program product, and a computer system for handling logical-to-physical table (LPT) entries. A computer implements a class of metadata including a logical-to-physical table (LPT) and LPT entries corresponding to the class of metadata. A computer caches, from the logical-to-physical translation layer, selected metadata blocks in a non-durable cache, the selected metadata blocks being selected from the class of metadata. A computer reduces a size of the selected metadata blocks by encoding the LPT entries from the non-durable cache during write operations to a flash memory. A computer records a location in flash memory of the encoded LPT entries in the logical-to-physical translation layer.
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公开(公告)号：US20240071542A1
公开(公告)日：2024-02-29
申请号：US17821608
申请日：2022-08-23
发明人： Radu Ioan Stoica , Roman Alexander Pletka , Nikolas Ioannou , Nikolaos Papandreou , Charalampos Pozidis , Timothy J. Fisher , Aaron Daniel Fry
CPC分类号： G11C29/021 , G11C29/52
摘要： Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.
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公开(公告)号：US11908531B2
公开(公告)日：2024-02-20
申请号：US17495574
申请日：2021-10-06
发明人： Nikolaos Papandreou , Roman Alexander Pletka , Radu Ioan Stoica , Nikolas Ioannou , Charalampos Pozidis , Timothy J. Fisher , Aaron Daniel Fry
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/32 , G11C16/3404 , G11C16/3495
摘要： A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.
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公开(公告)号：US11861175B2
公开(公告)日：2024-01-02
申请号：US17654328
申请日：2022-03-10
发明人： Radu Ioan Stoica , Aaron Daniel Fry , Nikolas Ioannou , Nikolaos Papandreou , Roman Alexander Pletka , Charalampos Pozidis , Jenny L Brown
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0679
摘要： A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.
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公开(公告)号：US11762569B2
公开(公告)日：2023-09-19
申请号：US16667702
申请日：2019-10-29
发明人： Radu Ioan Stoica , Roman Alexander Pletka , Timothy Fisher , Nikolaos Papandreou , Sasa Tomic , Nikolas Ioannou , Aaron Daniel Fry , Charalampos Pozidis , Andrew D. Walls
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F9/3004 , G06F12/0246 , G06F2209/5011
摘要： A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.
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公开(公告)号：US11302403B2
公开(公告)日：2022-04-12
申请号：US17149592
申请日：2021-01-14
发明人： Nikolaos Papandreou , Charalampos Pozidis , Nikolas Ioannou , Roman Alexander Pletka , Radu Ioan Stoica , Sasa Tomic , Timothy Fisher , Aaron Daniel Fry
摘要： A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
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公开(公告)号：US20210134377A1
公开(公告)日：2021-05-06
申请号：US16669264
申请日：2019-10-30
发明人： Nikolaos Papandreou , Charalampos Pozidis , Nikolas Ioannou , Roman Alexander Pletka , Radu Ioan Stoica , Sasa Tomic , Aaron Daniel Fry , Timothy Fisher
摘要： A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page. An attempt is made to read the calibrated given page, and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block. The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made. In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent.
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公开(公告)号：US20210124685A1
公开(公告)日：2021-04-29
申请号：US16663211
申请日：2019-10-24
发明人： Nikolaos Papandreou , Charalampos Pozidis , Roman Alexander Pletka , Sasa Tomic , Nikolas Ioannou , Radu Ioan Stoica
IPC分类号： G06F12/0882 , G06F12/02 , G06F12/06 , G06F11/07 , G11C11/409
摘要： A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.
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公开(公告)号：US11875831B2
公开(公告)日：2024-01-16
申请号：US17562772
申请日：2021-12-27
发明人： Roman Alexander Pletka , Radu Ioan Stoica , Nikolas Ioannou , Nikolaos Papandreou , Charalampos Pozidis , Timothy J. Fisher , Aaron Daniel Fry
摘要： A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.
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公开(公告)号：US20220415424A1
公开(公告)日：2022-12-29
申请号：US17355720
申请日：2021-06-23
发明人： Nikolaos Papandreou , Nikolas Ioannou , Roman Alexander Pletka , Radu Ioan Stoica , Charalampos Pozidis , Timothy J. Fisher , Andrew D. Walls
摘要： A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.
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