Hybrid molds for molten solder screening process
    1.
    发明申请
    Hybrid molds for molten solder screening process 失效
    熔融焊料筛选工艺的混合模具

    公开(公告)号:US20020125402A1

    公开(公告)日:2002-09-12

    申请号:US10128210

    申请日:2002-04-23

    Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer. The encasing is performed on a leveling fixture such that the top surface of the silicon face plate and the top surface of the extender material after solidification are perfectly leveled.

    Abstract translation: 公开了用于模制用于熔融焊料筛选过程的多个焊球的混合模具和用于制备这种模具的方法。 利用用于通过沿着特定结晶平面各向异性蚀刻晶体硅衬底而形成金字塔形状的多个空腔的方法来形成本发明混合模具中使用的结晶硅面板。 在一个优选的实施例中,硅面板通过粘合方法以一种确保在硅面板和玻璃背板的顶表面之间实现共面性的方法结合到硼硅酸盐玻璃背板上。 在替代实施例中,另外的玻璃框架用于将硅面板粘合到玻璃背板,再次确保硅面板的顶表面和玻璃框架之间的共面性。 在第二替代实施例中,硅面板封装在可以是硼硅酸盐玻璃或聚合物的增量材料中。 在平整装置上进行包装,使得硅面板的顶表面和固化后的增量材料的顶表面完美平整。

    Integrated toroidal coil inductors for IC devices
    3.
    发明申请
    Integrated toroidal coil inductors for IC devices 有权
    用于IC器件的集成环形线圈电感器

    公开(公告)号:US20030011041A1

    公开(公告)日:2003-01-16

    申请号:US10238746

    申请日:2002-09-10

    Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    Abstract translation: 提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。 线圈的非嵌入部分被制造为BEOL金属化层的一部分。 这允许螺线管的大的横截面积的匝数,从而减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面,所以线圈可以制造成具有大的电感值,并且占据芯片的小面积。 所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔,然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。 在平坦化之后,螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分(即,作为BEOL的线/通路)。 为了进一步增加螺线管线圈的横截面,可以通过电沉积通过BEOL层顶部的掩模来构建。

    Integrated coil inductors for IC devices

    公开(公告)号:US20020130386A1

    公开(公告)日:2002-09-19

    申请号:US09808381

    申请日:2001-03-14

    Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

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