公开(公告)号：US20180314462A1

公开(公告)日：2018-11-01

申请号：US15581729

申请日：2017-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/3855 ,  G06F13/1642

Abstract: A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.

公开(公告)号：US20180293188A1

公开(公告)日：2018-10-11

申请号：US15800863

申请日：2017-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42

Abstract: A computer-implemented method is provided for exclusive control of shared memory objects. The method computer-implemented includes transmitting and performing a plurality of accesses to the shared memory objects from local and remote locations via read requests and write requests made to a memory, and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list. The computer-implemented method further includes initiating each read request to the memory via the memory controller whatever the corresponding lock bit is, initiating each write request to the memory from the recently read location via the memory controller when the corresponding lock bit is enabled, otherwise notify the requesting local or remote locations as incomplete, and enabling and disabling the corresponding lock bit after the initiation of the read and write requests to the memory, respectively.

公开(公告)号：US10082974B2

公开(公告)日：2018-09-25

申请号：US14924774

申请日：2015-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama ,  Daiju Nakano ,  Kohji Takano

IPC: H04L29/06 ,  G06F3/06 ,  H04L29/08 ,  H04W24/04 ,  H04W76/25 ,  H04W76/19

CPC classification number: G06F3/0623 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0685 ,  H04L65/4084 ,  H04L65/4092 ,  H04L67/327 ,  H04W24/04 ,  H04W76/15 ,  H04W76/19 ,  H04W76/25 ,  H04W76/30

Abstract: Embodiments include providing content requested by a user via an access point capable of wireless communication. Aspects include receiving the content provided by the management server and storing the content provided by the management server into a volatile memory provided in the wireless communication apparatus. Aspects also include storing difference data into a nonvolatile memory if it is requested to change the content stored in the volatile memory and monitoring a state of communication connection with the access point and whether or not a packet giving an instruction to hold the content has been received. Aspects further include deleting the content stored in the volatile memory if communication with the access point is disconnected or if the packet is unreceived.

公开(公告)号：US20180095878A1

公开(公告)日：2018-04-05

申请号：US15281239

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F12/084 ,  G06F12/14 ,  G06F15/173

CPC classification number: G06F9/52 ,  G06F13/16 ,  G06F13/1642

Abstract: A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages from a first location to a second location via read requests and write requests made to a memory and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit. The computer-implemented method further includes initiating the read requests from the memory via the memory controller when associated lock bits are enabled and initiating the write requests from the memory via the memory controller when associated lock bits are disabled. The computer-implemented method further includes enabling and disabling the lock bits after the initiation of the write and read requests, respectively.

公开(公告)号：US20160156425A1

公开(公告)日：2016-06-02

申请号：US14947032

申请日：2015-11-20

Applicant: International Business Machines Corporation

Inventor： Yasunao Katayama ,  Yasuteru Kohda ,  Daiju Nakano ,  Kohji Takano

IPC: H04B17/345 ,  H04W24/02

CPC classification number: H04B17/345 ,  H04B17/102 ,  H04W24/02

Abstract: Wireless communication system, control apparatus, optimization method, wireless communication apparatus and program for optimizing a beam configuration of an area that is configured by dividing a wireless communication network. The wireless system includes a control apparatus and multiple wireless links which are arranged in an area where the control apparatus is in charge of optimizing a beam configuration. The control apparatus includes: a section for setting an antenna parameter for multiple wireless links in the area the control apparatus is in charge of, in accordance with a search algorithm; and section for evaluating the antenna parameter set by the setting section on the basis of radiation of electromagnetic waves.

Abstract translation: 无线通信系统，控制装置，优化方法，无线通信装置和程序，用于优化通过划分无线通信网络配置的区域的波束配置。 无线系统包括控制装置和多个无线链路，其布置在控制装置负责优化波束配置的区域中。 控制装置包括：根据搜索算法，在控制装置负责的区域中设定多个无线链路的天线参数的部分; 以及用于基于电磁波的辐射来评估由设置部分设置的天线参数的部分。

公开(公告)号：US09066289B2

公开(公告)日：2015-06-23

申请号：US13890338

申请日：2013-05-09

Applicant: International Business Machines Corporation

Inventor： Yasunao Katayama ,  Yasushi Negishi ,  Atsuya Okazaki

IPC: H04J3/06 ,  H04W56/00 ,  H04L12/721 ,  H04W40/02 ,  H04W40/06

CPC classification number: H04W56/00 ,  H04J3/0658 ,  H04L45/40 ,  H04W40/02 ,  H04W40/06

Abstract: A system including multiple nodes performing radio communication, wherein each node stores routing information, uses it to determine a transmission path, and performs cut-through transmission by transmitting and receiving packets to and from a node on the determined path through transmission and reception radio waves given a directivity by controlling their phases. In the system, time synchronization and transmission and reception of packet communication records are performed during a certain time period by carrying out the cut-through transmission while controlling phases of the radio waves so that all of the nodes form one or more closed loops. The node transmits and receives packets in accordance with routing information and a time frame assigned to each of the nodes as a time when each node is allowed to transmit and receive a packet, updates the routing information, and shares it with each node.

Abstract translation: 一种包括执行无线电通信的多个节点的系统，其中每个节点存储路由信息，使用它来确定传输路径，并且通过发送和接收无线电波通过在确定的路径上的节点发送和接收分组来执行直通传输 通过控制它们的阶段给出方向性。 在该系统中，通过在控制无线电波的相位的同时执行直通传输，使得所有节点形成一个或多个闭环，在一定时间段内执行分组通信记录的时间同步和发送和接收。 节点根据路由信息和分配给每个节点的时间帧发送和接收分组，作为允许每个节点发送和接收分组的时间，更新路由信息，并与每个节点共享。

公开(公告)号：US20140120903A1

公开(公告)日：2014-05-01

申请号：US13661750

申请日：2012-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas C. M. Fuller ,  Yasunao Katayama ,  Arun S. Natarajan

IPC: H04W52/04

CPC classification number: H04W52/04 ,  H04B17/382 ,  H04W16/18 ,  H04W52/143 ,  H04W52/225 ,  H04W52/265 ,  H04W52/386 ,  H04W52/44

Abstract: The present disclosure relates generally to the field of base station power control in a mobile network. In various examples, base station power control in a mobile network may be implemented in the form of systems, methods and/or algorithms.

Abstract translation: 本公开一般涉及移动网络中的基站功率控制领域。 在各种示例中，移动网络中的基站功率控制可以以系统，方法和/或算法的形式实现。

公开(公告)号：US20140075250A1

公开(公告)日：2014-03-13

申请号：US14038906

申请日：2013-09-27

Applicant: International Business Machines Corporation

Inventor： Yasunao Katayama ,  Seiji Munetoh ,  Nobuyuki Ohba ,  Tadayuki Okada ,  Atsuya Okazaki

IPC: G06F11/07

CPC classification number: G11C8/18 ,  G06F11/073 ,  G06F11/076 ,  G06F11/30 ,  G06F11/3037 ,  G06F11/3075 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

公开(公告)号：US10209925B2

公开(公告)日：2019-02-19

申请号：US15837992

申请日：2017-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/38

Abstract: A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.

公开(公告)号：US20180307604A1

公开(公告)日：2018-10-25

申请号：US15495145

申请日：2017-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yasunao Katayama

IPC: G06F12/0817 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F2212/60 ,  G06F2212/621

Abstract: Methods and systems for memory-side shared caching include determining whether a requested memory access is directed to shared portion of memory by referencing a lock address list in a memory controller. If the requested memory access is for the shared portion of memory, it is determined whether an associated data object is present in a memory-side cache. If the associated data object is present in the memory-side cache, the memory-side cache is accessed. If the associated data object is not present in the memory-side cache, an external memory is accessed.