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    Distribution of power vias in a multi-layer circuit board
    1.
    发明授权
    Distribution of power vias in a multi-layer circuit board 有权
    在多层电路板中分配电源通孔

    公开(公告)号：US09594865B2

    公开(公告)日：2017-03-14

    申请号：US14717026

    申请日：2015-05-20

    Applicant: International Business Machines Corporation

    Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

    IPC: G06F17/50 ,  H05K3/00

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

    Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

    Abstract translation: 一个方面是一种方法，其包括通过在电路设计系统的处理器上执行的电力通过放置工具来识别基于设计文件的多层电路板的电压域的源极和接收器，该设计文件定义了 多层电路板。 确定支持从源到汇的最大电流需求的多个电源通孔。 在多层电路板的位置处确定多个电源通孔的位置，该位置通过源极和漏极之间的电力通孔形成通路，并具有基本上相等的总路径长度，通过在源极和漏极之间限定的每个总路径 通过至少一个电源通孔。 设计文件被修改为在位置包括电源通孔。

    INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO
    2.
    发明申请
    INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO 有权
    具有3：1信号对接率的互连阵列图案

    公开(公告)号：US20170048967A1

    公开(公告)日：2017-02-16

    申请号：US15336884

    申请日：2016-10-28

    Applicant: International Business Machines Corporation

    Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

    IPC: H05K1/02 ,  H01L23/66 ,  H01L23/528 ,  H01P3/08 ,  H01P3/02

    CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

    Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

    Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

    Implementing high-speed signaling via dedicated printed circuit-board media
    4.
    发明授权
    Implementing high-speed signaling via dedicated printed circuit-board media 有权

    公开(公告)号：US11076493B2

    公开(公告)日：2021-07-27

    申请号：US16038417

    申请日：2018-07-18

    Applicant: International Business Machines Corporation

    Inventor： Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

    IPC: H05K3/46 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36

    Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.

    Implementing high-speed signaling via dedicated printed circuit-board media
    5.
    发明授权
    Implementing high-speed signaling via dedicated printed circuit-board media 有权

    公开(公告)号：US10034393B2

    公开(公告)日：2018-07-24

    申请号：US14089084

    申请日：2013-11-25

    Applicant: International Business Machines Corporation

    Inventor： Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

    IPC: H05K3/46 ,  H05K3/36 ,  H05K1/14 ,  H05K1/02

    Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.

    DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD
    7.
    发明申请
    DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD 有权
    电力线在多层电路板中的分布

    公开(公告)号：US20160342724A1

    公开(公告)日：2016-11-24

    申请号：US14834767

    申请日：2015-08-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

    IPC: G06F17/50 ,  H05K3/00

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K1/0265 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0979

    Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

    Abstract translation: 一个方面是一种方法，其包括通过在电路设计系统的处理器上执行的电力通过放置工具来识别基于设计文件的多层电路板的电压域的源极和接收器，该设计文件定义了 多层电路板。 确定支持从源到汇的最大电流需求的多个电源通孔。 在多层电路板的位置处确定多个电源通孔的位置，该位置通过源极和漏极之间的电力通孔形成通路，并具有基本上相等的总路径长度，通过在源极和漏极之间限定的每个总路径 通过至少一个电源通孔。 设计文件被修改为在位置包括电源通孔。

    INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO
    9.
    发明申请
    INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO 有权
    具有3：1信号对接率的互连阵列图案

    公开(公告)号：US20160150638A1

    公开(公告)日：2016-05-26

    申请号：US14551185

    申请日：2014-11-24

    Applicant: International Business Machines Corporation

    Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

    IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08

    CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

    Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

    Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

    Packaging for Eight-Socket One-Hop SMP Topology
    10.
    发明申请
    Packaging for Eight-Socket One-Hop SMP Topology 有权
    八插座一跳SMP拓扑封装

    公开(公告)号：US20150177794A1

    公开(公告)日：2015-06-25

    申请号：US14136135

    申请日：2013-12-20

    Applicant: International Business Machines Corporation

    Inventor： John L. Colbert ,  Daniel M. Dreps ,  Paul M. Harvey ,  Rohan U. Mandrekar

    IPC: G06F1/18 ,  G06F17/50

    CPC classification number: H05K3/325 ,  G06F1/183 ,  G06F1/20 ,  H01L23/36 ,  H01L23/49827 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/15313 ,  H05K7/1061 ,  Y10T29/49128 ,  Y10T29/49169

    Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

    Abstract translation: 提供了一种用于打包多个套接字，一跳对称多处理器拓扑的机制。 该机构经由第一多个平面栅格阵列（LGA）连接器中的相应一个将第一多个处理器模块中的每一个连接到第一多插槽平面。 该机构经由第二多个LGA连接器将第一多插槽平面连接到再分配卡的第一侧。 该机构经由第三多个LGA连接器中的相应一个将第二多个处理器模块中的每一个连接到第二多插槽平面。 该机构经由第四多个LGA连接器将第二多插槽平面连接到再分配卡的第二侧。

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