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    Interconnect array pattern with a 3:1 signal-to-ground ratio
    3.
    发明授权
    Interconnect array pattern with a 3:1 signal-to-ground ratio 有权
    具有3：1信号对地比的互连阵列模式

    公开(公告)号：US09543241B2

    公开(公告)日：2017-01-10

    申请号：US14551185

    申请日：2014-11-24

    Applicant: International Business Machines Corporation

    Inventor： Zhaoqing Chen ,  Matteo Cocchini ,  Rohan U. Mandrekar ,  Tingdong Zhou

    IPC: H01L23/498 ,  H01L23/528 ,  H04B3/32 ,  H01P3/02 ,  H01P3/08 ,  H05K1/02 ,  H04B1/00

    CPC classification number: H01L23/49838 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6627 ,  H01P3/02 ,  H01P3/026 ,  H01P3/081 ,  H04B1/00 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0245

    Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

    Abstract translation: 包括多个互连件的电子设备以网格图案正交布置并均匀间隔第一距离，所述多个互连件包括：第一导体对，其具有沿第一方向彼此相邻布置的导体，所述第一方向定向 相对于正交栅格图案的对角线的第二导体对，具有基本上垂直于第一方向的第二方向彼此相邻布置的导体的第二导体对，第二导体对的每个导体与第一导体对的每个信号导体间隔开第一距离 导体对和第三导体对，其中导体在基本上平行于第一方向的第三方向上彼此相邻布置，第三导体对的每个导体与第二导体对的信号元件之一间隔开第一距离 。

    ELECTRONIC MODULE POWER SUPPLY
    4.
    发明申请
    ELECTRONIC MODULE POWER SUPPLY 有权
    电子模块电源

    公开(公告)号：US20140029221A1

    公开(公告)日：2014-01-30

    申请号：US14040659

    申请日：2013-09-28

    Applicant: International Business Machines Corporation

    Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

    IPC: H05K1/11

    CPC classification number: H05K1/112 ,  H05K1/0263 ,  H05K1/0296 ,  H05K1/115 ,  H05K3/3436 ,  H05K2201/0355 ,  H05K2201/1028 ,  Y10T29/49128 ,  Y10T29/49155

    Abstract: Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supplying power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

    Abstract translation: 可以根据各种技术向电子模块供电。 在一般的实施方案中，例如，用于向电子模块供电的系统可以包括印刷电路板，电子模块和导电箔。 板可以包括在第一侧上的多个接触位置，其中至少一个接触位置电耦合到通孔到板的第二侧。 电子模块可以电耦合到板的第一侧上的接触位置，并且通过电耦合到通孔的至少一个接触位置接收电力。 箔可以适于传送用于电子模块的电力并且电耦合到电路板的第二侧上至少通过电气耦合到接收用于电子模块的电力的接触位置的通孔。

    Electronic module power supply
    5.
    发明授权
    Electronic module power supply 有权

    公开(公告)号：US10765002B2

    公开(公告)日：2020-09-01

    申请号：US16446919

    申请日：2019-06-20

    Applicant: International Business Machines Corporation

    Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

    IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34

    Abstract: Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supplying power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

    Reducing power grid noise in a processor while minimizing performance loss
    10.
    发明授权
    Reducing power grid noise in a processor while minimizing performance loss 有权
    降低处理器中的电网噪声，同时最大限度地降低性能损失

    公开(公告)号：US09141421B2

    公开(公告)日：2015-09-22

    申请号：US13693386

    申请日：2012-12-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Lee E. Eisen ,  Michael S. Floyd ,  Thomas Strach ,  Huajun Wen ,  Tingdong Zhou

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F11/30

    CPC classification number: G06F9/46 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/329 ,  G06F11/3024 ,  G06F2201/86 ,  Y02D10/24

    Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

    Abstract translation: 在处理器的管理中，监视逻辑运行活动，以在共享共同供电轨的多个核心的采样窗口期间从低电平增加到高电平，沿着公共电源轨具有至少一个去耦电容器。 响应于在采样窗口期间检测从低电平到高电平的逻辑运算活动的增加，处理器将在较低活动期间内的核上执行的逻辑运算限制在低电平和低电平之间设置的逻辑运算电平 中等水平，中等水平是低水平和高水平之间的量。 响应于较低活动期结束，处理器逐渐减少逻辑运行的限制，以恢复正常运行。

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