公开(公告)号：US20240339368A1

公开(公告)日：2024-10-10

申请号：US18746015

申请日：2024-06-17

申请人： FUJIFILM Corporation

发明人： Atsushi NAKAMURA ,  Kosuke Yamashita ,  Kazuki Tomota

IPC分类号： H01L23/29 ,  C09J133/24 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/295 ,  C09J133/24 ,  H01L21/563 ,  H01L24/43 ,  H01L24/45 ,  H01L25/0657 ,  H01L2224/45016 ,  H01L2224/4502 ,  H01L2225/06513

摘要： There is provided a manufacturing method for a bonded body, comprising: preparing a substrate A having a surface on which a wiring line terminal is provided; forming a polyimide-containing precursor portion on the surface of the substrate A, where the wiring line terminal is provided on the surface of the substrate A; preparing a substrate B having a surface on which a wiring line terminal is provided; and bonding the surface of the substrate A, where the polyimide-containing precursor portion is provided on the surface of the substrate A, to the surface of the substrate B, where the wiring line terminal is provided on the surface of the substrate B, wherein a difference between a cyclization rate of a polyimide in the polyimide-containing precursor portion before the bonding of the surface of the substrate A and a cyclization rate of a polyimide in a polyimide-containing portion formed at a bonded portion after the bonding of the surface of the substrate A is 5% or more.

公开(公告)号：US20240128154A1

公开(公告)日：2024-04-18

申请号：US18531002

申请日：2023-12-06

申请人： FURUKAWA ELECTRIC CO., LTD.

发明人： Minoru MORITA

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3735 ,  H01L23/3731 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/45 ,  H01L25/0657 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/45005 ,  H01L2224/4502 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/04894 ,  H01L2924/0665 ,  H01L2924/351

摘要： Provided is a thermally conductive film-like adhesive capable of sufficiently advancing a curing reaction under milder conditions, capable of effectively suppressing residual voids between the adhesive and a wiring board in a semiconductor package to be obtained when used as a die attach film, and capable of obtaining a semiconductor package excellent in heat releasing property inside the package. In addition, provided are a semiconductor package using the thermally conductive film-like adhesive and a method of producing the same.

公开(公告)号：US20190221537A1

公开(公告)日：2019-07-18

申请号：US15980948

申请日：2018-05-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Han ZHONG ,  Yong Qiang TANG ,  Chen XIONG ,  Zi Qi WANG ,  Xi Lin LI

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/48 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/4502 ,  H01L2224/45124 ,  H01L2224/45565 ,  H01L2224/45647 ,  H01L2224/45664 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48724 ,  H01L2224/48769 ,  H01L2924/35121

摘要： A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond.

公开(公告)号：US20180174988A1

公开(公告)日：2018-06-21

申请号：US15899755

申请日：2018-02-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles L. ARVIN ,  Jeffrey P. GAMBINO ,  Charles F. MUSANTE ,  Christopher D. MUZZY ,  Wolfgang SAUTER

IPC分类号： H01L23/00 ,  C22C21/00

CPC分类号： H01L24/05 ,  C22C21/00 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05083 ,  H01L2224/05099 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05671 ,  H01L2224/4502 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01013

摘要： A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer.

公开(公告)号：US20160379936A1

公开(公告)日：2016-12-29

申请号：US15121419

申请日：2015-02-27

申请人： LFOUNDRY S.R.L.

发明人： Gerhard Spitzlsperger ,  Carsten Schmidt

IPC分类号： H01L23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L21/74 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78 ,  H01L29/739 ,  H01L29/732 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/562 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823418 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/43 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/808 ,  H01L2224/4502

摘要： A method of fabricating a semiconductor product includes processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface of the wafer. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes forming implantations from the backside of the wafer, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.

摘要翻译： 一种制造半导体产品的方法包括从前表面处理半导体晶片，所述前表面包括设置在与所述前表面相邻的所述晶片的所述基板中的结构，并且形成嵌入在所述晶片的前表面上的电介质层中的布线。 晶片在其前表面安装到载体晶片，使得可以从晶片的背面去除材料以使半导体晶片变薄。 半导体晶片的背面处理包括从晶片的背面形成注入，形成深沟槽以将结构与晶片内的其它结构隔离，形成通硅通孔以接触晶片前侧的特征，并形成主体 联系。 可以在同一晶片内产生多个器件。

公开(公告)号：US09530761B2

公开(公告)日：2016-12-27

申请号：US13597973

申请日：2012-08-29

申请人： Alan Roth ,  Eric Soenen ,  Chaohao Wang

发明人： Alan Roth ,  Eric Soenen ,  Chaohao Wang

IPC分类号： H05K7/00 ,  H01L25/16 ,  H05K1/18 ,  H01L23/00

CPC分类号： H02M3/158 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/29025 ,  H01L2224/2919 ,  H01L2224/32265 ,  H01L2224/4502 ,  H01L2224/45111 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0479 ,  H01L2924/048 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/10351 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/14252 ,  H01L2924/1427 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10166 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2924/00

摘要： A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.

摘要翻译： 封装系统包括设置在衬底上的至少一个有源电路。 钝化结构设置在至少一个有源电路上。 钝化结构具有至少一个开口，其被配置为暴露至少一个第一电垫。 在钝化结构上方设置至少一个无源电组件。 所述至少一个无源电部件与所述至少一个第一电焊盘电耦合。

公开(公告)号：US09293440B2

公开(公告)日：2016-03-22

申请号：US14134680

申请日：2013-12-19

申请人： The Charles Stark Draper Laboratory, Inc.

发明人： Michael Holm ,  Maurice Karpman ,  Matt Shea

IPC分类号： H01L23/495 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0655 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/43 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/4501 ,  H01L2224/45015 ,  H01L2224/4502 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/85399 ,  H01L2224/82 ,  H01L2924/20753

摘要： A method for interconnecting a die on a substrate of an electronic package. The method includes the steps of forming a plurality of free-end wire bonds on the die, wherein the free-end wire bonds are upstanding from the die, and encapsulating the free-end wire bonds in an encapsulation layer. Planarizing the encapsulation layer is performed so that the free-end wire bonds are exposed for electrical connection. Interconnecting the free-end wire bonds is provided by applying an interconnection layer on the encapsulation layer.

摘要翻译： 一种用于将电子封装的基板上的裸片互连的方法。 该方法包括以下步骤：在管芯上形成多个自由端引线键合，其中自由端引线键合从管芯直立，并将自由端引线键合封装在封装层中。 执行平坦化封装层，使得自由端引线接合被暴露用于电连接。 通过在封装层上施加互连层来提供互连自由端引线键合。

公开(公告)号：US20150102476A1

公开(公告)日：2015-04-16

申请号：US14367788

申请日：2012-08-31

申请人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

发明人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49524 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0311 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/43847 ,  H01L2224/4502 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85181 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/43

摘要： The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

摘要翻译： 本发明公开了一种四边形无铅封装及其制造方法。 四边形无铅封装包括由载体凹坑和布置在载体凹坑周围的三个引线组成的引线框载体，其中三个引线圈分别由相互断开的多个引线组成; IC芯片粘附在载体坑中; 并在所有的引线上镀上一个内引铅化学镍和斑铜矿镀层; 内部引线化学镍和长磷石镀层沿与IC芯片相同的方向排列; IC芯片通过接合线与内引线化学镍和卟啉镀层连接; 和IC芯片，镀有内引线化学镀镍和钯金属层的所有引线的端部和接合线全部封装在塑料封装中。 通过以下步骤制造四边形扁平无铅封装：薄片化和刻划晶片; 制造引线框架; 加载芯片; 执行压焊和塑料包装; 执行后固化; 打印; 电镀; 分离引线; 分离产品; 和测试/编织。 根据封装，解决了现有普通四边形无铅封装单面封装时引线少，焊丝长，焊接成本高，应用频率有限的问题。

公开(公告)号：US20240194580A1

公开(公告)日：2024-06-13

申请号：US18521001

申请日：2023-11-28

申请人： Infineon Technologies AG

发明人： Susanne Schulte ,  Scott David Wallace ,  Oliver Blank

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/45005 ,  H01L2224/4502 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/1306

摘要： A power semiconductor device includes a semiconductor substrate. A signal routing structure is disposed above the semiconductor substrate. The signal routing structure comprises a specific metal. A solderable power pad forms a power terminal of the power semiconductor device. The solderable power pad comprises the specific metal. An electrically insulating dielectric passivation layer is disposed between the solderable power pad and the signal routing structure.

公开(公告)号：US11887963B2

公开(公告)日：2024-01-30

申请号：US17187686

申请日：2021-02-26

申请人： KIOXIA CORPORATION

发明人： Kazuma Hasegawa

IPC分类号： H01L23/00 ,  H01L25/18

CPC分类号： H01L24/49 ,  H01L24/13 ,  H01L24/20 ,  H01L24/45 ,  H01L25/18 ,  H01L2224/13147 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/4502 ,  H01L2224/46 ,  H01L2924/1431 ,  H01L2924/1438

摘要： According to one embodiment, a semiconductor device includes a support and a stacked body on the support. The stacked body is formed of a plurality of semiconductor chips that are stacked on each other. The stacked body has a lower surface facing the support and an upper surface facing away from the support. A first wire is connected to one of the semiconductor chips in the stack and extends upward from the semiconductor chip to at least the height of the upper surface of the stacked body. A second wire is connected to the support and extends upward from the support to at least the height of the upper surface of the stacked body.