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    Field effect transistors and methods for fabricating the same
    1.
    发明授权
    Field effect transistors and methods for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US07605045B2

    公开(公告)日：2009-10-20

    申请号：US11457300

    申请日：2006-07-13

    申请人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    发明人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

    摘要： Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

    摘要翻译： 提供场效应晶体管和制造场效应晶体管的方法。 根据本发明的示例性实施例的方法包括形成覆盖硅衬底的多晶硅栅电极。 栅电极具有两个平行的侧壁。 在硅衬底上制造两个侧壁间隔物。 两个侧壁间隔物中的每一个具有与栅电极的两个平行侧壁中的一个相邻的侧壁。 去除两个侧壁间隔物之间​​的栅电极的一部分。

    FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME
    2.
    发明申请
    FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20080014704A1

    公开(公告)日：2008-01-17

    申请号：US11457300

    申请日：2006-07-13

    申请人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    发明人： Igor Peidous ,  Patrick Press ,  Rolf Stephan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

    摘要： Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

    摘要翻译： 提供场效应晶体管和制造场效应晶体管的方法。 根据本发明的示例性实施例的方法包括形成覆盖硅衬底的多晶硅栅电极。 栅电极具有两个平行的侧壁。 在硅衬底上制造两个侧壁间隔物。 两个侧壁间隔物中的每一个具有与栅电极的两个平行侧壁中的一个相邻的侧壁。 去除两个侧壁间隔物之间​​的栅电极的一部分。

    FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS
    6.
    发明申请
    FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS 审中-公开
    形成硅/碳源/排水区的硅表面

    公开(公告)号：US20070200176A1

    公开(公告)日：2007-08-30

    申请号：US11550631

    申请日：2006-10-18

    申请人： Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

    发明人： Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

    IPC分类号： H01L27/12

    CPC分类号： H01L29/458 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78687

    摘要： Formation of a silicide layer on the source/drain regions of a field effect transistor with a channel under tensile strain is disclosed. The strain is originated by the silicon/carbon source/drain regions which are grown by CVD deposition. In order to form the silicide layer, a silicon cap layer is deposited in situ by CVD. The silicon cap layer is then employed to form a silicide layer made of a silicon/cobalt compound. This method allows the formation of a silicide cobalt layer in silicon/carbon source/drain regions, which was until the present time not possible.

    摘要翻译： 公开了在具有拉伸应变的通道的场效应晶体管的源/漏区上形成硅化物层。 该菌株由通过CVD沉积生长的硅/碳源/漏区产生。 为了形成硅化物层，通过CVD原位沉积硅覆盖层。 然后使用硅覆盖层形成由硅/钴化合物制成的硅化物层。 该方法允许在硅/碳源/漏区中形成硅化钴钴层，直到目前为止不可能。

    Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill
    8.
    发明授权
    Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill 有权
    半导体器件包括替代栅电极结构和由后接触填充形成的自对准接触元件

    公开(公告)号：US08846513B2

    公开(公告)日：2014-09-30

    申请号：US13241915

    申请日：2011-09-23

    申请人： Peter Baars ,  Richard Carter ,  Rolf Stephan

    发明人： Peter Baars ,  Richard Carter ,  Rolf Stephan

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

    摘要翻译： 当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅 而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。 以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。 在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
    10.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20100203698A1

    公开(公告)日：2010-08-12

    申请号：US12763324

    申请日：2010-04-20

    申请人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

    摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。