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    FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS
    1.
    发明申请
    FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS 审中-公开
    形成硅/碳源/排水区的硅表面

    公开(公告)号：US20070200176A1

    公开(公告)日：2007-08-30

    申请号：US11550631

    申请日：2006-10-18

    申请人： Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

    发明人： Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

    IPC分类号： H01L27/12

    CPC分类号： H01L29/458 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78687

    摘要： Formation of a silicide layer on the source/drain regions of a field effect transistor with a channel under tensile strain is disclosed. The strain is originated by the silicon/carbon source/drain regions which are grown by CVD deposition. In order to form the silicide layer, a silicon cap layer is deposited in situ by CVD. The silicon cap layer is then employed to form a silicide layer made of a silicon/cobalt compound. This method allows the formation of a silicide cobalt layer in silicon/carbon source/drain regions, which was until the present time not possible.

    摘要翻译： 公开了在具有拉伸应变的通道的场效应晶体管的源/漏区上形成硅化物层。 该菌株由通过CVD沉积生长的硅/碳源/漏区产生。 为了形成硅化物层，通过CVD原位沉积硅覆盖层。 然后使用硅覆盖层形成由硅/钴化合物制成的硅化物层。 该方法允许在硅/碳源/漏区中形成硅化钴钴层，直到目前为止不可能。

    Field effect transistor and method of forming a field effect transistor
    2.
    发明授权
    Field effect transistor and method of forming a field effect transistor 有权
    场效应晶体管和形成场效应晶体管的方法

    公开(公告)号：US07629211B2

    公开(公告)日：2009-12-08

    申请号：US11684211

    申请日：2007-03-09

    申请人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/331 ,  H01L21/8234

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

    摘要翻译： 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

    FIELD EFFECT TRANSISTOR AND METHOD OF FORMING A FIELD EFFECT TRANSISTOR
    3.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF FORMING A FIELD EFFECT TRANSISTOR 有权
    场效应晶体管和形成场效应晶体管的方法

    公开(公告)号：US20080026531A1

    公开(公告)日：2008-01-31

    申请号：US11684211

    申请日：2007-03-09

    申请人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    发明人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

    IPC分类号： H01L21/8234 ,  H01L27/088

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

    摘要翻译： 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

    Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
    6.
    发明授权
    Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain 有权
    半导体器件包括具有嵌入的Si / Ge材料的NMOS和PMOS晶体管，用于产生拉伸和压缩应变

    公开(公告)号：US07893503B2

    公开(公告)日：2011-02-22

    申请号：US12754819

    申请日：2010-04-06

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same
    7.
    发明授权
    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same 有权
    包括具有应力沟道区域的场效应晶体管的半导体结构及其形成方法

    公开(公告)号：US07608499B2

    公开(公告)日：2009-10-27

    申请号：US11685847

    申请日：2007-03-14

    申请人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    发明人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

    摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件和第二晶体管元件中的每一个包括栅电极。 在第一晶体管元件和第二晶体管元件上沉积应力材料层。 被施加的材料层被加工成从与第二晶体管元件的栅电极相邻的应力材料层侧壁间隔和覆盖第一晶体管元件的硬掩模形成。 在第二晶体管元件的栅电极附近形成一对空腔。 在空腔中形成一对应力产生元件，并且至少部分地去除硬掩模。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    9.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20080099794A1

    公开(公告)日：2008-05-01

    申请号：US11748902

    申请日：2007-05-15

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L29/04 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些说明性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN
    10.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
    包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件

    公开(公告)号：US20110104878A1

    公开(公告)日：2011-05-05

    申请号：US13005676

    申请日：2011-01-13

    申请人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    发明人： Sven Beyer ,  Manfred Horstmann ,  Patrick Press ,  Wolfgang Buchholtz

    IPC分类号： H01L21/20

    CPC分类号： H01L21/823807 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849

    摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

    摘要翻译： 通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变， 可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。 在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。 因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。