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    Method for evaluating scratch resistance of plastic resins
    1.
    发明授权
    Method for evaluating scratch resistance of plastic resins 有权
    评估塑料树脂耐刮擦性的方法

    公开(公告)号：US08266944B2

    公开(公告)日：2012-09-18

    申请号：US12478811

    申请日：2009-06-05

    申请人： Kee Hae Kwon ,  Il Jin Kim ,  Hyung Rang Moon ,  Jae Bum Park ,  Seong Ho Kong ,  O Sung Kwon

    发明人： Kee Hae Kwon ,  Il Jin Kim ,  Hyung Rang Moon ,  Jae Bum Park ,  Seong Ho Kong ,  O Sung Kwon

    IPC分类号： G01N3/56

    CPC分类号： G01N3/46

    摘要： Disclosed herein is a method for evaluating scratch resistance of a plastic resin comprising scratching a surface of a test sample of plastic resin using a scratch apparatus to form a scratch of the surface having a scratch profile; scanning the scratched test sample with a surface profile analysis apparatus to measure the scratch profile; and creating a scratch resistance evaluation index based on the measured scratch profile to evaluate the scratch resistance of the test sample. The method has good reliability and reproducibility, reduces measurement time and errors caused by measurers and measuring conditions, provides easy measurement and can be widely applied to all plastic resins.

    摘要翻译： 本发明公开了一种用于评价塑料树脂的耐刮擦性的方法，包括使用刮擦装置刮擦塑料树脂的测试样品的表面以形成具有划痕轮廓的表面的划痕; 用表面轮廓分析装置扫描划痕的测试样品以测量划痕; 以及基于所测量的刮擦轮廓来产生耐擦伤性评估指数，以评估测试样品的耐擦伤性。 该方法具有良好的可靠性和可重复性，减少测量时间和测量误差，测量条件，提供易于测量，可广泛应用于所有塑料树脂。

    Thermoplastic nanocomposite resin composite materials
    2.
    发明授权
    Thermoplastic nanocomposite resin composite materials 有权
    热塑性纳米复合材料复合材料

    公开(公告)号：US08262939B2

    公开(公告)日：2012-09-11

    申请号：US11477758

    申请日：2006-06-29

    申请人： Il Jin Kim ,  O Sung Kwon ,  Jae Bum Park

    发明人： Il Jin Kim ,  O Sung Kwon ,  Jae Bum Park

    IPC分类号： H01B1/00

    CPC分类号： C08F8/42 ,  C08F292/00 ,  C08L51/10 ,  C08L55/02 ,  Y10T428/31663 ,  C08L2666/02 ,  C08L2666/24

    摘要： A polymer composite material includes metal (oxide) nanoparticles chemically bonded to a vinyl polymer. Some embodiments may additionally comprise thermoplastic resin through which the nanoparticles and vinyl polymer are dispersed. In some embodiments, the composite materials have improved impact strength, tensile strength, heat resistance, and flexural modulus.

    摘要翻译： 聚合物复合材料包括化学键合到乙烯基聚合物上的金属（氧化物）纳米颗粒。 一些实施方案可另外包含分散有纳米颗粒和乙烯基聚合物的热塑性树脂。 在一些实施方案中，复合材料具有改进的冲击强度，拉伸强度，耐热性和挠曲模量。

    Method for Evaluating Scratch Resistance of Plastic Resins
    3.
    发明申请
    Method for Evaluating Scratch Resistance of Plastic Resins 有权
    评估塑料树脂耐划伤性的方法

    公开(公告)号：US20090293585A1

    公开(公告)日：2009-12-03

    申请号：US12478811

    申请日：2009-06-05

    申请人： Kee Hae KWON ,  Il Jin Kim ,  Hyung Rang Moon ,  Jae Bum Park ,  Seong Ho Kong ,  O Sung Kwon

    发明人： Kee Hae KWON ,  Il Jin Kim ,  Hyung Rang Moon ,  Jae Bum Park ,  Seong Ho Kong ,  O Sung Kwon

    IPC分类号： G01N3/56

    CPC分类号： G01N3/46

    摘要： Disclosed herein is a method for evaluating scratch resistance of a plastic resin comprising scratching a surface of a test sample of plastic resin using a scratch apparatus to form a scratch of the surface having a scratch profile; scanning the scratched test sample with a surface profile analysis apparatus to measure the scratch profile; and creating a scratch resistance evaluation index based on the measured scratch profile to evaluate the scratch resistance of the test sample. The method has good reliability and reproducibility, reduces measurement time and errors caused by measurers and measuring conditions, provides easy measurement and can be widely applied to all plastic resins.

    摘要翻译： 本发明公开了一种用于评价塑料树脂的耐刮擦性的方法，包括使用刮擦装置刮擦塑料树脂的测试样品的表面以形成具有划痕轮廓的表面的划痕; 用表面轮廓分析装置扫描划痕的测试样品以测量划痕; 以及基于所测量的刮擦轮廓来产生耐擦伤性评估指数，以评估测试样品的耐擦伤性。 该方法具有良好的可靠性和可重复性，减少测量时间和测量误差，测量条件，提供易于测量，可广泛应用于所有塑料树脂。

    Methods of fabricating semiconductor devices and structures thereof
    4.
    发明授权
    Methods of fabricating semiconductor devices and structures thereof 有权
    制造半导体器件的方法及其结构

    公开(公告)号：US07659561B2

    公开(公告)日：2010-02-09

    申请号：US12133231

    申请日：2008-06-04

    申请人： O Sung Kwon

    发明人： O Sung Kwon

    IPC分类号： H01L29/76

    CPC分类号： H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843 ,  Y10S257/90

    摘要： Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material.

    摘要翻译： 公开了在半导体器件的特征的侧壁上形成间隔物的方法及其结构。 优选实施例包括半导体器件，其包括工件和设置在工件上方的至少一个特征。 第一间隔件设置在至少一个特征的侧壁上，第一间隔件包括第一材料。 第一衬垫设置在第一间隔物上方，并且在靠近第一间隔物的工件的一部分上方，第一衬垫包括第一材料。 第二间隔件设置在第一衬垫上，第二间隔件包括第二材料。 第二衬垫设置在第二间隔件上，第二衬垫包括第一材料。

    METHOD AND STRUCTURE FOR FORMING SILICIDE CONTACTS ON EMBEDDED SILICON GERMANIUM REGIONS OF CMOS DEVICES
    5.
    发明申请
    METHOD AND STRUCTURE FOR FORMING SILICIDE CONTACTS ON EMBEDDED SILICON GERMANIUM REGIONS OF CMOS DEVICES 审中-公开
    CMOS器件嵌入式硅锗区域形成硅化物接触的方法与结构

    公开(公告)号：US20080070360A1

    公开(公告)日：2008-03-20

    申请号：US11533018

    申请日：2006-09-19

    申请人： Oh-Jung Kwon ,  O Sung Kwon

    发明人： Oh-Jung Kwon ,  O Sung Kwon

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein the faceted surfaces are disposed adjacent shallow trench isolation (STI) regions used to separate NFET regions from PFET regions of the CMOS device; depositing a metal layer for silicide formation over the CMOS device; and annealing the CMOS device to form silicide, wherein the protective layer formed over the faceted surfaces prevents the formation of silicide thereon.

    摘要翻译： 形成用于互补金属氧化物半导体（CMOS）器件的硅化物触点的方法包括在衬底的嵌入式SiGe（eSiGe）区域的刻面上选择性地形成保护层，eSiGe区域包括PFET部分中的压应力诱导层 其中所述刻面被设置在用于将NFET区与CMOS器件的PFET区分离的浅沟槽隔离（STI）区域附近; 在CMOS器件上沉积用于硅化物形成的金属层; 并且对CMOS器件进行退火以形成硅化物，其中形成在刻面上的保护层防止其上形成硅化物。

    Method for forming photoresist patterns
    6.
    发明授权
    Method for forming photoresist patterns 失效
    光刻胶图形形成方法

    公开(公告)号：US5858590A

    公开(公告)日：1999-01-12

    申请号：US959961

    申请日：1997-10-24

    申请人： O Sung Kwon ,  Doo Hee Lee ,  Hyung Sun Yook ,  Heung Gee Hong ,  Young Mo Goo

    发明人： O Sung Kwon ,  Doo Hee Lee ,  Hyung Sun Yook ,  Heung Gee Hong ,  Young Mo Goo

    IPC分类号： G03F7/20 ,  G03F1/00 ,  G03F7/26 ,  H01L21/027 ,  G03C5/00

    CPC分类号： G03F7/70625 ,  G03F7/20

    摘要： A method for forming photoresist patterns by performing a photolithograpy process by the unit of a predetermined number of wafers, wherein the photoresist patterns are formed under a condition that an exposure time taken to fore each of the photoresist patterns is predetermined taking into consideration a variation in reflection factor, on the basis of the following equation:Z=X+{(r-a).times.(Y-X)/(.beta.-.alpha.)}where, "T" represents a reference thickness corresponding to a thickness of a photoresist film to be patterned to form a corresponding one of the photoresist patterns, exhibiting a minimum reference factor or a maximum reference factor, "T'" a thickness limit more than the reference thickness (T), ".alpha." a reference reflection factor at the reference thickness (T), ".beta." a reflection factor limit at the thickness limit (T'), "r" a varied reflection factor, "X" a reference exposure time at the reference reflection factor (.alpha.), "Y" an exposure time limit at the reflection factor limit (.beta.), and "Z" the varied exposure time.

    摘要翻译： 通过以预定数量的晶片为单位执行光刻处理来形成光致抗蚀剂图案的方法，其中在考虑到每个光致抗蚀剂图案之前的曝光时间是预定的条件下形成光致抗蚀剂图案， 反射因子，基于以下等式：Z = X + {（ra）x（YX）/（β-α）}其中，“T”表示对应于待图案化的光致抗蚀剂膜的厚度的参考厚度 形成对应的一个光致抗蚀剂图案，其具有最小参考因子或最大参考因子，“T”“厚度限制大于参考厚度（T），”α“是参考厚度（T）处的参考反射系数， ，“β”是厚度极限（T'）处的反射因子极限，“r”是反射因子，“X”是参考反射系数（α）时的参考曝光时间，“Y” 反射 因子限制（β）和“Z”变化的曝光时间。

    METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION
    8.
    发明申请
    METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION 失效
    通过在金属沉积期间增加放射量的量来制备硅化物的方法

    公开(公告)号：US20110070732A1

    公开(公告)日：2011-03-24

    申请号：US12563459

    申请日：2009-09-21

    申请人： Oh-Jung Kwon ,  Anthony G. Domenicucci ,  O Sung Kwon ,  Jin-Woo Choi

    发明人： Oh-Jung Kwon ,  Anthony G. Domenicucci ,  O Sung Kwon ,  Jin-Woo Choi

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28518 ,  C23C14/18 ,  C23C14/5806 ,  H01L21/2855

    摘要： A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.

    摘要翻译： 提供一种用于形成金属半导体合金的方法，其包括提供包括铂源和镍源的沉积设备，其中所述铂源与所述镍源分离; 将具有半导体表面的基板定位在沉积设备中; 在半导体表面上形成金属合金，其中形成金属合金包括沉积阶段，其中铂源以最初的速率以最初的速率将铂沉积到半导体表面上，该初始时间段大于最终时间段的最终时间 沉积阶段，镍源将镍沉积到半导体表面; 并退火金属合金以使镍和铂与半导体衬底反应以提供镍铂半导体合金。

    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance
    9.
    发明申请
    Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance 有权
    形成具有低接触电阻的硅化源/漏极触点的场效应晶体管的方法

    公开(公告)号：US20090239344A1

    公开(公告)日：2009-09-24

    申请号：US12402816

    申请日：2009-03-12

    申请人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    发明人： Yong Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    IPC分类号： H01L21/335 ,  H01L21/28

    CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

    摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。