公开(公告)号：US09406393B2

公开(公告)日：2016-08-02

申请号：US14668043

申请日：2015-03-25

Applicant: Ilhan Park ,  Ji-Suk Kim ,  Jung-Ho Song ,  Yang-Lo Ahn

Inventor： Ilhan Park ,  Ji-Suk Kim ,  Jung-Ho Song ,  Yang-Lo Ahn

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2211/5621

Abstract: A program verification method is for a nonvolatile memory device which programs a plurality of memory cells. The program verification method includes applying a plurality of verification voltages, and determining whether programming of memory cells, having different target threshold voltage distributions, from among the plurality of memory cells is completed based on one of the plurality of verification voltages.

Abstract translation: 程序验证方法是用于对多个存储器单元进行编程的非易失性存储器件。 程序验证方法包括应用多个验证电压，并且基于多个验证电压中的一个来确定具有不同目标阈值电压分布的存储单元的编程是否从多个存储单元中的一个完成。

公开(公告)号：US09183943B2

公开(公告)日：2015-11-10

申请号：US14104406

申请日：2013-12-12

Applicant: Yang-Lo Ahn ,  Sang-Wan Nam ,  Sang-Won Shim

Inventor： Yang-Lo Ahn ,  Sang-Wan Nam ,  Sang-Won Shim

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/3422

Abstract: A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings. The vertical nonvolatile memory device is configured to apply the non-selection read voltage to at least one unselected word line of the cell string a desired time period after the applying of the non-selection read voltage to the at least one selection line.

Abstract translation: 提供一种垂直非易失性存储装置，其包括在与基板相交的方向上形成的多个单元串。 垂直非易失性存储器件被配置为向多个单元串中的连接到单元串的至少一个选择线施加非选择读取电压。 垂直非易失性存储器件被配置为在将非选择读取电压施加到至少一个选择线之后的所需时间周期内将非选择读取电压施加到单元串的至少一个未选择的字线。

公开(公告)号：US09196364B2

公开(公告)日：2015-11-24

申请号：US14244930

申请日：2014-04-04

Applicant: Minsu Kim ,  Yang-Lo Ahn ,  Dae Han Kim ,  Kitae Park

Inventor： Minsu Kim ,  Yang-Lo Ahn ,  Dae Han Kim ,  Kitae Park

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/3427

Abstract: A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.

Abstract translation: 非易失性存储器件包括以三维（3D）结构排列的多个垂直NAND闪存单元，设置在3D结构中并具有由第一地选择线和第二地选择线选择的存储单元的第一存储块， 其中所述第一和第二接地选择线彼此电分离，设置在所述3D结构中并具有由第三选择线和第四选择线选择的存储单元的第二存储器块，其中所述第三和第四接地选择线被电分离 以及传递驱动信号以通过响应于块选择信号接通分别连接到第一和第三接地选择线的接地选择晶体管的传输晶体管。